Abstract: A method for designing integrated circuits may include custom designing, at the transistor level, individual cells to be incorporated into cell-based macros. A macro-level function of an integrated circuit's design specification requiring custom, transistor-level design may be identified and custom cells may be designed at the transistor-level to meet the design specification. Custom designed cells may be included in cell-based macros, thus allowing cell-based simulation and verification methodologies and tools to be used on the integrated circuit design. Static timing analysis, circuit extraction and other characteristics may be defined for each custom cell and the timing analysis and circuit extraction for cell-based macros may be defined based on the timing and extraction information for the custom cells included in the macro.

Abstract: A floating point processor for pipelining a series of calculations of simple and compound arithmetic operations includes at least one arithmetic operation unit for performing arithmetic operations on input operands provided to the arithmetic operation units and at least one accumulator for storing the results of the arithmetic operations performed by the arithmetic operation unit. The results stored in the accumulators are then provided to the arithmetic operation units. Arithmetic operations are pipelined through the floating point processor by a series of latches which sequence the input operands, results produced by the arithmetic operation units using the input operands, and results produced by the arithmetic operation units using the input operands and the accumulated operands.

Abstract: An electronic digital processor system including an internal memory means further including an electrically programmable read-only memory for the storage of data and commands which define operations on the data. Also included is an arithmetic and logic unit for performing operations on the data and a register set for temporary storage of data and addresses. Further included is a plurality of data paths which couple the internal memory with the arithmetic and logic unit and registers. Control and timing circuitry is provided for the execution of commands that access the memory and arithmetic and logic unit by the registers and for the execution of commands for programming the electrically programmable read-only memory.

Abstract: A video system controller allows for the transfer of data between a display memory and a microprocessor that is used to control the controller and from the display memory to a CRT monitor. The transfer operations are controlled by the video system controller through a state machine that is configured with a plurality of standard cells connected in cascade arrangement, which can be configured as either a Moore or a Mealy state machine. Each state machine has a programmable logic array in which timing signals, when applied thereto, will cause a predetermined output to appear on the output on each of the standard cells. A logic means, depending upon whether the machine is a Moore type state machine or a Mealy type state machine logically manipulates the output of the programmable logic array to obtain the state output for that particular cell.

Abstract: A video memory and display (CRT) controller circuit on a single semiconductor substrate controls a DRAM (dynamic random access memory) used as a video memory and a CRT display. The video memory and display controller is normally a part of a video system which includes a data processor, video memory and a CRT display. The video memory and display controller includes a row address latch for storing a row address, a column address latch for storing a column address, display address logic which generates row and column addresses for display update ad refresh logic which generates row addresses for the required periodic DRAM refresh. A multiplexer provides the application of the proper address to the address bus of the DRAM. The display controller circuit is responsive to the data processor data bus for generating display control signals for control of the CRT display.

Abstract: A video system has a controller for controlling the transfer of data from a processor to a CRT monitor. The controller has two clocks and a CRT interface for synchronously interfacing the controller to the CRT monitor, a second interface for synchronously interfacing the controller to the processor. A first clock source provides timing for the CRT interface and is in synch with the timing of the CRT monitor. A second clock source provides timing for the processor interphase which is in synch with the timing of the processor.

Abstract: A video system is able to change the display on a video monitor with a minimal number of memory transfer cycles. The video system includes a monitor for displaying of processed data, a processor means for processing the data to be displayed, a display memory means divided into a plurality of planes addressable by a row address, the display memory stores the data that has been processed by the processor means. There are additional other sources of data which is processed by the processor means for storing in the display memory and subsequently being displayed by the CRT monitor . A control means controls the data transfer between the data sources, the processor, the display memories, and the CRT monitor and includes a row address override circuit. The row address override circuit comprises a plurality of output logic for providing a write enable signal to a memory plane. Each memory plane is connected to a cross finding output logic circuit.

Abstract: A video memory controller controls a DRAM (dynamic random access memory) used as a video memory and as a system memory. The video memory and the video memory controller are normally a part of a video system which includes a data processor, the video memory, the video memory controller, a CRT controller and a CRT display device. The video memory controller includes a row address latch for storing a row address from the data processor, a column address latch for storing a column address from the data processor, a refresh address register for storing a memory refresh address and a display update generator for sequentially generating the addresses necessary for update of the CRT display. A multiplexer couples the proper address to the video memory under control of a memory cycle generator which generates the timing of the memory refresh and display update. An arbiter device enables only one of the possible memory cycles at a time.

Abstract: A video system has a processor processing of data to be displayed on a CRT monitor. A memory which is the embodiment shown is a multiport dynamic random accessed memory, stores the data therein according to X and Y coordinates. A video controller controls the transfer of data between the processor and the memory; the controller also, has included therein an X and Y address logic for providing the X and Y coordinates to the memory.

Abstract: An electrically programmable read-only memory including a memory array of several bits capable of storing binary data connected to an address circuit for accepting a plurality of bits that designate a selected set of the memory array bits and further connected to a data latch to store data to be programmed in a selected set of memory bits. Further provided is a high voltage circuit for providing a high voltage to the selected set of bits according to the data in the data latch and for programming the data in the selected set of memory array bits. Further provided is an output circuit to provide a precharge signal to the memory array bits and to output data programmed in a selected set of memory array bits designated by the address circuit.

Abstract: An electronic digital processor system including an internal memory, an arithmetic and logic unit, registers, peripheral control circuitry providing an internal mode, an external mode, emulator mode, data paths, and control and timing circuitry. In the internal mode, the data and the commands are stored in the internal memory. In the external mode, the commands which control the operations of the microcomputer are stored in the external memory. In the emulator mode, the user can combine the microcomputer with external devices to emulate a composite system with minimal hardware. The emulator mode would also allow the user to develop software for the composite system.

Abstract: A electronic digital processor system input/output circuitry including several input/output data ports where each port contains receiving circuitry to receive bit data from bit data pads and transmitting circuitry to transmit bit data to the data bit pads and control circuitry that provides for a configuration where one input/output port may respond to the address of another input/output port, allowing the second input/output port to perform other functions. This capability would allow a user to execute a program that emulates one configuration while the actual, physical connection of devices is, in fact, another configurations. The input/output circuitry also include control circuitry that determines whether the port is to receive bit data or to transmit bit data. This circuitry is connected to a data bus that couples the input/output data ports to the remaining electronic digital processor system.