Abstract: Embodiments of systems, apparatuses, and methods for performing a blend instruction in a computer processor are described. In some embodiments, the execution of a blend instruction causes a data element-by-element selection of data elements of first and second source operands using the corresponding bit positions of a writemask as a selector between the first and second operands and storage of the selected data elements into the destination at the corresponding position in the destination.

Abstract: Embodiments of systems, apparatuses, and methods for performing an expand and/or compress instruction in a computer processor are described. In some embodiments, the execution of an expand instruction causes the selection of elements from a source that are to be sparsely stored in a destination based on values of the writemask and store each selected data element of the source as a sparse data element into a destination location, wherein the destination locations correspond to each writemask bit position that indicates that the corresponding data element of the source is to be stored.

Abstract: The present invention relates to a method and system for providing a load with conditional fault instruction that includes an associated conditional operator, which enables load operations to be advanced above program branches by the compiler without causing unwarranted fault conditions. Specifically, the load instruction can be executed out of normal program order to enable information to be retrieved from memory before the information is needed, to permit the retrieved information to begin to be used before the conditional operator can be evaluated. Likewise, a dynamically scheduled processor can advance components of the instruction and further improve performance without having faults effect the normal program flow. The load instruction can stop the use of the information and replace the information with a predetermined, generally deterministic, value if the conditional operator indicates a faulty load operation.

Abstract: Method for producing a predetermined length page memory pointer record, according to a selected page size and a selected page address, the method including the procedures of: determining a dynamic location of a separator bit within the page memory pointer record, according to the selected page size and an initial page size, the initial page size being respective of the smallest page size in a given memory system, writing a predetermined value to the dynamic location, writing a sequence of values opposite to the predetermined value to selected page size bits of the page memory pointer record, when the selected page size is different than the initial page size, and writing the selected page address to selected page address bits of the page memory pointer record.

Abstract: Method for producing a predetermined length page memory pointer record, according to a selected page size and a selected page address, the method including the procedures of: determining a dynamic location of a separator bit within the page memory pointer record, according to the selected page size and an initial page size, the initial page size being respective of the smallest page size in a given memory system, writing a predetermined value to the dynamic location, writing a sequence of values opposite to the predetermined value to selected page size bits of the page memory pointer record, when the selected page size is different than the initial page size, and writing the selected page address to selected page address bits of the page memory pointer record.

Abstract: The present invention relates to a method and system for providing a load with conditional fault instruction that includes an associated conditional operator, which enables load operations to be advanced above program branches by the compiler without causing unwarranted fault conditions. Specifically, the load instruction can be executed out of normal program order to enable information to be retrieved from memory before the information is needed, to permit the retrieved information to begin to be used before the conditional operator can be evaluated. Likewise, a dynamically scheduled processor can advance components of the instruction and further improve performance without having faults effect the normal program flow. The load instruction can stop the use of the information and replace the information with a predetermined, generally deterministic, value if the conditional operator indicates a faulty load operation.

Abstract: An apparatus includes a data array, control logic, an entry candidate table, and a future target table. The control logic is coupled to the data array and adapted to store at least one trace segment of instructions into the data array. The entry candidate table is coupled to the control logic and is adapted to store offset information related to the position of a selected instruction within the trace segment. The future target table is coupled to the control logic and adapted to store a potential entry point into the trace segment. A method for caching instructions includes storing a first plurality of instructions in a first trace segment. A control flow instruction is identified from the first plurality of instructions and the outcome of the control flow instruction is predicted. The control flow instruction has a predicted taken target address and a predicted not-taken target address corresponding to the outcome predicted. The predicted not-taken target address is stored.

Abstract: An apparatus includes a data array and control logic. The control logic is coupled to the data array and adapted to store at least one trace segment of instructions into the data array. The control logic allows the instructions of the trace segment to be sequentially retrieved beginning with a selected instruction. The selected instruction is offset from the first instruction of the trace segment. A method for caching instructions includes storing a first plurality of instructions in a first trace segment. A selected instruction of the first plurality of instructions is identified within the first trace segment. The selected instruction is offset from the first instruction of the first trace segment. The offset information related to the position of the selected instruction within the first trace segment is stored.

Abstract: The invention in several embodiments includes an apparatus and a method for predicting whether store instructions can be safely executed out-of-order. The apparatus, includes at least one execution unit, a reorder buffer adapted to holding a plurality of instructions from an instruction sequence for execution by the execution units, and a memory storage device adapted to holding a collision history table. The collision history table has entries for load instructions of the instruction sequence Each of the entries is adapted to predicting when the associated load instruction is colliding.

Abstract: An advanced register renamer comprises an associative memory having a plurality of entries, each entry storing a representation of a single operation as an expression paired with a corresponding name. The expression and the name are respectively stored in first and second fields of an entry in the memory. Both fields are available for subsequent assembly level operations to use as pattern matches. A means for converting a subsequent operation in the stream to a new operation searches for a match between an expression of the subsequent operation and the first field of a matching entry. Upon finding a match with the expression field in the table, the subsequent operation is renamed to a new operation by replacing the expression with the corresponding name field of the matching entry taken from the associative memory.

Abstract: The present disclosure is directed to a portable elongate frame made of multiple lengthwise stringers which support the pipe testing apparatus. The frame has upper and lower stringers which are laced together by cross connected braces, and said stringers assemble into an elongate structure having first and second carriages at opposite ends thereof. The two carriages support first and second test heads for the pin and box of the joint. They are equipped with resilient members which squeeze against the pipe, contact the joint on the interior on the pin end, and on the exterior at the coupling at the box end. The structure is formed of multiple lengthwise stringers, the stringers at one side being hinged, and the stringers at the opposite side being released by a latch means to enable the structure to be folded into two equal portions for easy mounting behind a tow vehicle connected therewith by a V-shaped trailer hitch.