Abstract: An electronic circuit generates a bias current that is proportional to a frequency of a reference clock signal in a switched capacitor circuit. The electronic circuit includes a capacitive circuit selectively coupled to a transistor supplied by a voltage reference circuit. During a first phase the capacitive circuit is charged by a current from the transistor, and during the second phase the capacitive circuit is discharged to ground. The duration of each phase is related to the reference clock signal. The average current corresponds to a bias signal and is filtered to reduce ripple in the bias signal before the bias signal is received by the switched capacitor circuit. The capacitive circuit is configured with a first and second capacitor arranged in a complimentary out-of-phase configuration. During a first phase, the first capacitor is charged and the second capacitor is discharged. During the second phase, the second capacitor is charged and the first capacitor is discharged.

Abstract: A comparator circuit includes a regenerative stage that uses a relatively small quiescent current combined with a relatively large dynamic current to charge a common-source node in the regenerative stage. The quiescent current helps maintain the common-source node in the regenerative stage near a desired charged level. The comparator circuit can also include an input isolation circuit to eliminate charge kick-back to the input signal lines.

Abstract: An amplifier circuit for amplifying a difference between first and second input signals which is capable of precharge a node at which the second input signal is present thereby enhancing the speed of operation. The circuit includes a first amplifier stage and a capacitor having one terminal coupled to the amplifier stage input. Switching circuit, typically in the form of various transistor switches, operates to switch the first input signal to the second terminal of capacitor. The amplifier stage output is then coupled to the second node thereby charging the node to a voltage approximately equal to input signal voltage. The second input signal is then coupled to the precharged second node. Assuming that the second signal magnitude is related to the magnitude of the first input signal, as it would be in certain Analog-To-Digital Converter applications, the second signal will be able to rapidly change the voltage from the first input signal voltage level to the second input voltage level.

Abstract: An input switch for use in a switch-capacitor circuit having unified architecture, and a switch-capacitor circuit including such an input switch, an amplifier, a capacitor between the amplifier and switch, and at least one NMOS transistor. The input switch samples an input potential in a sampling mode, receives a reference potential, and includes a transmission gate having a first NMOS transistor. The switch is configured to prevent the transmission gate from passing the reference to the capacitor when the reference is so low that the difference between the sampled input and reference is below an overdrive-causing level, thereby preventing capacitor charge loss which would otherwise lead to overdrive while the switch-capacitor circuit compares the reference with the sampled input.

Abstract: An amplifier circuit having a reset capability for use in analog-to-digital converter comparator stages and the like. First and second amplifier stages include first and transistor second switches, respectively, which are coupled between the amplifier inputs and outputs. A capacitor is coupled intermediate the output of the first amplifier stage and the input of the second amplifier stage. A third transistor switch is coupled between the output of the second amplifier stage and the output of the first amplifier stage. In an initialize state, a switch controller operates to render the first and second switches conductive and the third switch non-conductive. In a typical application, this will cause a charge to be stored on the capacitor indicative of any offset between the virtual grounds of the amplifier stages. In a reset state, the third switch is conductive and the first and second switches are made non-conductive.

Abstract: A comparator circuit and method for comparing first and second inputs. First and second input capacitors are provided for storing first and second voltages indicative of the first and second inputs when the circuit is in a sample phase. A comparator stage coupled to the first and second input capacitors switches from a measure state to one of first and second output states when the comparator circuit is in a hold phase based upon the relative magnitudes of the first and second inputs. Reset circuitry operates to discharge the input capacitors when the comparator stage switches to one of the output states. During a subsequent sample phase, the discharged input capacitors can be rapidly charged to new voltages thereby increasing the operating speed of the comparator circuit.