Abstract: A system and method for identifying latent reliability defects (LRD) in semiconductor devices are configured to perform one or more stress tests with one or more stress test tools on at least some of a plurality of wafers received from one or more in-line sample analysis tools to determine a passing set of the plurality of wafers and a failing set of the plurality of wafers, perform a reliability hit-back analysis on at least some of the failing set of the plurality of wafers, analyze the reliability hit-back analysis to determine one or more geographic locations of one or more die fail chains caused by one or more latent reliability defects (LRD), and perform a geographic hit-back analysis on the one or more geographic locations of the one or more die fail chains caused by the LRD.

Abstract: An inspection system may include a controller communicatively coupled to one or more in-line sample analysis tools including, but not limited to, an inspection tool or a metrology tool. The controller may identify defects in a population of dies based on data received from at least one of the one or more in-line sample analysis tools, assign weights to the identified defects indicative of predicted impact of the identified defects on reliability of the dies using a weighted defectivity model, generate defectivity scores for the dies in the population by aggregating the weighted defects in the respective dies in the population, and determine a set of outlier dies based on the defectivity scores for the dies in the population, wherein at least some of the set of outlier dies are isolated from the population.

Abstract: A system and method for identifying latent reliability defects (LRD) in semiconductor devices are configured to perform one or more stress tests with one or more stress test tools on at least some of a plurality of wafers received from one or more in-line sample analysis tools to determine a passing set of the plurality of wafers and a failing set of the plurality of wafers, perform a reliability hit-back analysis on at least some of the failing set of the plurality of wafers, analyze the reliability hit-back analysis to determine one or more geographic locations of one or more die fail chains caused by one or more latent reliability defects (LRD), and perform a geographic hit-back analysis on the one or more geographic locations of the one or more die fail chains caused by the LRD.

Abstract: An inspection system may include a controller communicatively coupled to one or more in-line sample analysis tools including, but not limited to, an inspection tool or a metrology tool. The controller may identify defects in a population of dies based on data received from at least one of the one or more in-line sample analysis tools, assign weights to the identified defects indicative of predicted impact of the identified defects on reliability of the dies using a weighted defectivity model, generate defectivity scores for the dies in the population by aggregating the weighted defects in the respective dies in the population, and determine a set of outlier dies based on the defectivity scores for the dies in the population, wherein at least some of the set of outlier dies are isolated from the population.

Abstract: Methods and systems for inline parts average testing and latent reliability defect recognition or detection are disclosed. An inline parts average testing method may include: performing inline inspection and metrology on a plurality of wafers at a plurality of critical steps during wafer fabrication; aggregating inspection results obtained from inline inspection and metrology utilizing one or more processors to obtain a plurality of aggregated inspection results for the plurality of wafers; identifying one or more statistical outliers among the plurality of wafers at least partially based on the plurality of aggregated inspection results obtained for the plurality of wafers; and disqualifying the one or more statistical outliers from entering a supply chain for a downstream manufacturing process, or segregating the one or more statistical outliers for further evaluation, testing or repurposing.

Abstract: Methods and systems for inline parts average testing and latent reliability defect recognition or detection are disclosed. An inline parts average testing method may include: performing inline inspection and metrology on a plurality of wafers at a plurality of critical steps during wafer fabrication; aggregating inspection results obtained from inline inspection and metrology utilizing one or more processors to obtain a plurality of aggregated inspection results for the plurality of wafers; identifying one or more statistical outliers among the plurality of wafers at least partially based on the plurality of aggregated inspection results obtained for the plurality of wafers; and disqualifying the one or more statistical outliers from entering a supply chain for a downstream manufacturing process, or segregating the one or more statistical outliers for further evaluation, testing or repurposing.