Abstract: The present disclosure generally relates to semiconductor processing for a bipolar junction transistor (BJT). In an example, a semiconductor device includes a semiconductor substrate, a multi-depth isolation structure in the semiconductor substrate, and a BJT on the semiconductor substrate. The multi-depth isolation structure includes a first isolation portion in the semiconductor substrate and a second isolation portion in the semiconductor substrate. The first isolation portion is to a first depth in the semiconductor substrate. The second isolation portion is to a second depth in the semiconductor substrate. The first depth is deeper in the semiconductor substrate than the second depth. The BJT includes a collector region and a base layer. The collector region is in the semiconductor substrate laterally between the first isolation portion and the second isolation portion. The base layer is on the collector region and over and adjoining the first isolation portion and the second isolation portion.

Abstract: Semiconductor devices and fabrication methods thereof are described. For example, a semiconductor device includes a semiconductor layer, a source region disposed in the semiconductor layer, a drain region disposed in the semiconductor layer, a gate electrode, and an insulating layer disposed between a portion of the gate electrode and the semiconductor layer. The insulating layer has a first sidewall extending toward the source region and a second sidewall extending toward the drain region, the first sidewall having a first slope and the second sidewall having a second slope greater than the first slope.

Abstract: Semiconductor devices and fabrication methods thereof are described. For example, a semiconductor device includes a semiconductor layer, a source region disposed in the semiconductor layer, a drain region disposed in the semiconductor layer, an insulating layer disposed in the semiconductor layer between the source region and the drain region, and a gate disposed over the semiconductor layer between the source region and the drain region, the gate covering a portion of the insulating layer. The insulating layer has a first sidewall extending toward the source region and a second sidewall extending toward the drain region, the first sidewall having a first slope and the second sidewall having a second slope greater than the first slope.

Abstract: The present disclosure generally relates to semiconductor processing integration for a bipolar junction transistor (BJT). In an example, a semiconductor device includes a semiconductor substrate, a bipolar junction transistor (BJT), a field effect transistor (FET), and a composite structure. The semiconductor substrate includes a BJT region, a complementary FET (CFET) region, and a transition region between the BJT region and the CFET region. The BJT is on the semiconductor substrate in the BJT region. The FET is on the semiconductor substrate in the CFET region. The composite structure is on the semiconductor substrate in the transition region. The composite structure includes a dielectric material. The dielectric material has a sidewall proximate and facing the CFET region and has a top surface that forms at least a portion of an upper surface of the composite structure.

Abstract: In one example, a method of forming an electronic device includes receiving a semiconductor substrate having a dielectric layer located over an emitter region of a partially formed bipolar junction transistor. A sacrificial layer is formed over the dielectric layer. A resist layer is formed over the sacrificial layer. A first pattern is formed in the resist layer including a resist layer sidewall over the emitter region. A second pattern is formed in the sacrificial layer. The second pattern includes a sacrificial layer sidewall aligned with the resist layer sidewall. The second pattern is transferred to the dielectric layer.

Abstract: The present disclosure generally relates to semiconductor processing integration for a bipolar junction transistor (BJT). In an example, a semiconductor device includes a semiconductor substrate, an etch stop layer, a pedestal dielectric layer, a BJT, and a field effect transistor (FET). The semiconductor substrate includes a BJT region and a complementary FET (CFET) region. The etch stop layer is over the semiconductor substrate in the BJT region. The pedestal dielectric layer is over the etch stop layer in the BJT region. The BJT is on the semiconductor substrate in the BJT region. At least a first portion of the BJT is in an opening through the pedestal dielectric layer and the etch stop layer. At least a second portion of the BJT is further over the pedestal dielectric layer. The FET is on the semiconductor substrate in the CFET region.

Abstract: The present disclosure generally relates to semiconductor processing for a bipolar junction transistor (BJT). In an example, a semiconductor device includes a semiconductor substrate and a bipolar junction transistor on the semiconductor substrate. The bipolar junction transistor includes a collector layer on the semiconductor substrate, a base layer on the collector layer, a raised base layer on the base layer, a dielectric spacer on the base layer and along a sidewall of the raised base layer, and an emitter layer on the base layer. The dielectric spacer is laterally between the raised base layer and the emitter layer. The emitter layer extends over the dielectric spacer and at least partially over the raised base layer. The raised base layer has a substantially continuous upper surface from a distance away from the emitter layer to the dielectric spacer underlying the emitter layer.

Abstract: An integrated circuit (IC) device including one or more corrugated channel structures formed in or over a semiconductor substrate, where a corrugated channel structure includes a first sidewall, a second sidewall and a top surface. In an example, the corrugated channel structure is provided with a substantially uniform distribution profile of a dopant across a horizontal plane from the first sidewall to the second sidewall.

Abstract: An integrated circuit (IC) device including one or more corrugated channel structures formed in or over a semiconductor substrate, where a corrugated channel structure includes modified first and second sidewalls and a modified top surface. In an example, the corrugated channel structure is provided with a substantially uniform distribution profile of a dopant across a horizontal plane from the modified first sidewall to the modified second sidewall.

Abstract: The present disclosure generally relates to semiconductor processing integration for a bipolar junction transistor (BJT). In an example, a semiconductor device includes a semiconductor substrate, a BJT, a field effect transistor (FET), and a composite structure. The semiconductor substrate includes a BJT region, a complementary FET (CFET) region, and a transition region between the BJT region and the CFET region. The BJT is on the semiconductor substrate in the BJT region. The FET is on the semiconductor substrate in the CFET region. The composite structure is on the semiconductor substrate in the transition region. The composite structure includes a material that is the same as a gate electrode of the FET.

Abstract: The present disclosure generally relates to an integrated circuit (IC) including a flash memory bit structure. In an example, an IC includes a flash memory bit structure and a transistor structure. The flash memory bit structure is on a semiconductor substrate. The flash memory bit structure includes a word line structure and a first oxide layer disposed between the semiconductor substrate and the word line structure. The first oxide layer is free of nitridation. The transistor structure is on the semiconductor substrate. The transistor structure includes a gate structure and a gate oxide layer including nitridation. The gate oxide layer is over the semiconductor substrate. The gate structure is over the gate oxide layer.

Abstract: The present disclosure generally relates to semiconductor processing integration for a bipolar junction transistor (BJT). In an example, a semiconductor device includes a semiconductor substrate, a pedestal dielectric layer, a collector layer, a base layer, and an emitter layer. The semiconductor substrate includes a bipolar junction transistor region. The pedestal dielectric layer is in the bipolar junction transistor region and is over an upper surface of the semiconductor substrate. The collector layer is on the upper surface of the semiconductor substrate and is through the pedestal dielectric layer. The base layer is on the collector layer and an upper surface of the pedestal dielectric layer. The pedestal dielectric layer extends laterally over the upper surface of the semiconductor substrate from the base layer. The emitter layer is on the base layer.

Abstract: An integrated circuit (IC) including Flash memory cells with self-aligned floating gates and a method of fabrication thereof is disclosed. A floating gate (FG) layer of polysilicon is deposited and patterned to form FG structures as part of a masking block used in forming isolation trenches. A dielectric fill material fills the isolation trenches. Subsequently, the dielectric fill material is removed using a CMP process that is configured to stop on the polysilicon of the FG structures.

Abstract: A method of forming an integrated circuit includes forming a first trench that extends into the semiconductor substrate. A silicon nitride layer is deposited over the semiconductor substrate. The silicon nitride layer extends into the first trench. A second trench is formed that extends through the silicon nitride layer into the semiconductor substrate. The second trench is spaced apart from the first trench. An oxide layer is formed that fills the second trench. The silicon nitride layer outside the first trench is removed.

Abstract: Methods, systems, and devices supporting configurable resistivities for lines in a memory device, such as access lines in a memory array are described. For example, metal lines at different levels of a memory device may be oxidized to different extents in order for the lines at different levels of the memory device to have different resistivities. This may allow the resistivity of lines to be tuned on a level-by-level basis without altering the fabrication techniques and related parameters used to initially form the lines at the different levels, which may have benefits related to at least reduced cost and complexity. Lines may be oxidized to a controlled extent using either a dry or wet process.

Abstract: Methods, systems, and devices supporting configurable resistivities for lines in a memory device, such as access lines in a memory array are described. For example, metal lines at different levels of a memory device may be oxidized to different extents in order for the lines at different levels of the memory device to have different resistivities. This may allow the resistivity of lines to be tuned on a level-by-level basis without altering the fabrication techniques and related parameters used to initially form the lines at the different levels, which may have benefits related to at least reduced cost and complexity. Lines may be oxidized to a controlled extent using either a dry or wet process.

Abstract: Methods, systems, and devices supporting configurable resistivities for lines in a memory device, such as access lines in a memory array are described. For example, metal lines at different levels of a memory device may be oxidized to different extents in order for the lines at different levels of the memory device to have different resistivities. This may allow the resistivity of lines to be tuned on a level-by-level basis without altering the fabrication techniques and related parameters used to initially form the lines at the different levels, which may have benefits related to at least reduced cost and complexity. Lines may be oxidized to a controlled extent using either a dry or wet process.

Abstract: Methods, systems, and devices supporting configurable resistivities for lines in a memory device, such as access lines in a memory array are described. For example, metal lines at different levels of a memory device may be oxidized to different extents in order for the lines at different levels of the memory device to have different resistivities. This may allow the resistivity of lines to be tuned on a level-by-level basis without altering the fabrication techniques and related parameters used to initially form the lines at the different levels, which may have benefits related to at least reduced cost and complexity. Lines may be oxidized to a controlled extent using either a dry or wet process.

Abstract: Methods, systems, and devices supporting configurable resistivities for lines in a memory device, such as access lines in a memory array are described. For example, metal lines at different levels of a memory device may be oxidized to different extents in order for the lines at different levels of the memory device to have different resistivities. This may allow the resistivity of lines to be tuned on a level-by-level basis without altering the fabrication techniques and related parameters used to initially form the lines at the different levels, which may have benefits related to at least reduced cost and complexity. Lines may be oxidized to a controlled extent using either a dry or wet process.