Patents by Inventor Robert Cassel

Robert Cassel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230114440
    Abstract: Methods, systems, and devices supporting configurable resistivities for lines in a memory device, such as access lines in a memory array are described. For example, metal lines at different levels of a memory device may be oxidized to different extents in order for the lines at different levels of the memory device to have different resistivities. This may allow the resistivity of lines to be tuned on a level-by-level basis without altering the fabrication techniques and related parameters used to initially form the lines at the different levels, which may have benefits related to at least reduced cost and complexity. Lines may be oxidized to a controlled extent using either a dry or wet process.
    Type: Application
    Filed: October 21, 2022
    Publication date: April 13, 2023
    Inventors: Koushik Banerjee, Isaiah O. Gyan, Robert Cassel, Jian Jiao, William L. Cooper, Jason R. Johnson, Michael P. O'Toole
  • Patent number: 11495293
    Abstract: Methods, systems, and devices supporting configurable resistivities for lines in a memory device, such as access lines in a memory array are described. For example, metal lines at different levels of a memory device may be oxidized to different extents in order for the lines at different levels of the memory device to have different resistivities. This may allow the resistivity of lines to be tuned on a level-by-level basis without altering the fabrication techniques and related parameters used to initially form the lines at the different levels, which may have benefits related to at least reduced cost and complexity. Lines may be oxidized to a controlled extent using either a dry or wet process.
    Type: Grant
    Filed: February 4, 2020
    Date of Patent: November 8, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Koushik Banerjee, Isaiah O. Gyan, Robert Cassel, Jian Jiao, William L. Cooper, Jason R. Johnson, Michael P. O'Toole
  • Publication number: 20210241828
    Abstract: Methods, systems, and devices supporting configurable resistivities for lines in a memory device, such as access lines in a memory array are described. For example, metal lines at different levels of a memory device may be oxidized to different extents in order for the lines at different levels of the memory device to have different resistivities. This may allow the resistivity of lines to be tuned on a level-by-level basis without altering the fabrication techniques and related parameters used to initially form the lines at the different levels, which may have benefits related to at least reduced cost and complexity. Lines may be oxidized to a controlled extent using either a dry or wet process.
    Type: Application
    Filed: February 4, 2020
    Publication date: August 5, 2021
    Inventors: Koushik Banerjee, Isaiah O. Gyan, Robert Cassel, Jian Jiao, William L. Cooper, Jason R. Johnson, Michael P. O'Toole
  • Patent number: 4604285
    Abstract: Known disadvantages of protein Ca are overcome or reduced by acylating the protein to form a derivative which will gradually hydrolyse in vivo to regenerate the active enzyme. The enzyme derivative comprises protein Ca in which the active site essential for anti-coagulant activity is blocked by an acyl group removable in vivo by enzymatic hydrolysis to provide a sustained and controlled release of protein Ca, preferred acyl groups being optionally substituted benzoyl or acryloyl groups.
    Type: Grant
    Filed: March 18, 1985
    Date of Patent: August 5, 1986
    Assignee: Beecham Group p.l.c.
    Inventors: Richard A. Smith, Robert Cassels