Abstract: The amount of jitter incurred when reading data written into a FIFO can be reduced by clocking the FIFO with Read Clock pulses at a frequency ? ƒn where ? is a whole integer and ƒn is the frequency at which the memory is clocked to write data. Read Addresses are applied to the FIFO at a frequency on the order of ƒn to identify successive locations in the memory for reading when the memory is clocked with read clocked pulses to enable reading of samples stored at such successive locations. The duration of at least one successive Read Addresses is altered in response to memory usage status to maintain memory capacity below a prescribed threshold.