Abstract: A multiple output video camera employs a multi-tap memory access system, in which an image input DMA master writes frames of a source image at a maximum frame rate and maximum resolution, via an image bus and a memory controller, into an image memory. In the multi-tap multiple access memory system, a plurality of concurrent independent video output circuits, each possess an image bus input/output master coupled to the image bus; an independent video signal processing circuit; and an output circuit that provides an independently processed version of the sequential video images to a respective output port. The outputs can be digital or analog.

Abstract: A method for rotating an input image matrix having pixel grouping data to form an output image matrix in a computer is provided. The pixel grouping data is accessed and readdressed to rotate the input image matrix. The pixel grouping data is desampled into desampled pixel grouping data. At least one line of the desampled pixel grouping data is sorted into a plurality of groups of desampled pixel grouping data. A first group of the desampled pixel grouping data is written to a first line of the output image matrix. A second group of the desampled pixel grouping data is written to a second line of the output image matrix. Preferably, the pixel grouping data represents subsampled color image data in L*a*b* space. The method takes advantage of the bandwidth of high-performance busses in direct memory access systems to rotate data in real-time.

Abstract: A plurality of input/output connector modules are located along a time multiplex bus. Each module has a plurality of programmable cells comprised of digital components. Each cell can be electronically programmed to receive one bit of information. These bits of information are used by each module to determine the address and input/output configuration assumed by the module. Programming data is sent via a serial input data (SID) line to the programming cells. The SID line has a plurality of delays which are located between the modules. The delays allow all of the programming cells of one module to be programmed before the next module receives the data along the SID line. The delays are created by the intrinsic resistance of the SID line and capacitors connected to the SID line which cause a delay in the programming data. The SID line is also clamped to ground out the programming signals after each cell has been programmed.