Abstract: A shock strut is provided that includes a first energy absorption stage or load limiter and a second energy absorption stage or load limiter. The second energy absorption stage or load limiter can include one or more disc springs. The shock strut can be employed on both fixed and retractable landing gear alike, while providing design adjustability for obtaining load-deflection curves that accommodate a range of descent or impact velocities.

Abstract: An eye-tracking device and associated software together allow a patient to communicate with health-care providers (HCPs), family members, and other individuals via eye gaze technology. The system presents the patient with a hierarchical and intuitive set of graphical menus that, for example, allow the patient, via his or her eye-gaze location, to indicate basic needs (e.g., food, bathroom, bed adjustment), alert the nursing staff to an emergency situation, and/or indicate pain level associated with a specific part of the patient's body. In parallel, an administrator of the system may use traditional touch screen functionality to assist in calibration, select patient preferences, and otherwise configure the system for use. In yet another embodiment, improved systems and methods are provided for performing eye-tracking using a variety of machine learning techniques instead of, or in addition to, traditional geometric methods.

Abstract: A shock strut is provided that includes a first energy absorption stage or load limiter and a second energy absorption stage or load limiter. The second energy absorption stage or load limiter can include one or more disc springs. The shock strut can be employed on both fixed and retractable landing gear alike, while providing design adjustability for obtaining load-deflection curves that accommodate a range of descent or impact velocities.

Abstract: Embodiments of an invention for virtualization exceptions are disclosed. In one embodiment, a processor includes instruction hardware, control logic, and execution hardware. The instruction hardware is to receive a plurality of instructions, including an instruction to enter a virtual machine. The control logic is to determine, in response to a privileged event occurring within the virtual machine, whether to generate a virtualization exception. The execution hardware is to generate a virtualization exception in response to the control logic determining to generate a virtualization exception.

Abstract: Methods and apparatus for approximation using polynomial functions are disclosed. In one embodiment, a processor comprises decoding and execution circuitry. The decoding circuitry is to decode an instruction, where the instruction comprises a first operand specifying an output location and a second operand specifying a plurality of data element values to be computed. The execution circuitry is to execute the decoded instruction. The execution includes to compute a result for each of the plurality of data element values using a polynomial function to approximate a complex function, where the computation uses coefficients stored in a lookup location for the complex function, and where data element values within different data element value ranges use different sets of coefficients. The execution further includes to store results of the computation in the output location.

Abstract: Embodiments of an invention for virtualization exceptions are disclosed. In one embodiment, a processor includes instruction hardware, control logic, and execution hardware. The instruction hardware is to receive a plurality of instructions, including an instruction to enter a virtual machine. The control logic is to determine, in response to a privileged event occurring within the virtual machine, whether to generate a virtualization exception. The execution hardware is to generate a virtualization exception in response to the control logic determining to generate a virtualization exception.

Abstract: Embodiments of an invention for virtualization exceptions are disclosed. In one embodiment, a processor includes instruction hardware, control logic, and execution hardware. The instruction hardware is to receive a plurality of instructions, including an instruction to enter a virtual machine. The control logic is to determine, in response to a privileged event occurring within the virtual machine, whether to generate a virtualization exception. The execution hardware is to generate a virtualization exception in response to the control logic determining to generate a virtualization exception.

Abstract: Embodiments of an invention for virtualization exceptions are disclosed. In one embodiment, a processor includes instruction hardware, control logic, and execution hardware. The instruction hardware is to receive a plurality of instructions, including an instruction to enter a virtual machine. The control logic is to determine, in response to a privileged event occurring within the virtual machine, whether to generate a virtualization exception. The execution hardware is to generate a virtualization exception in response to the control logic determining to generate a virtualization exception.

Abstract: Embodiments of an invention for virtualization exceptions are disclosed. In one embodiment, a processor includes instruction hardware, control logic, and execution hardware. The instruction hardware is to receive a plurality of instructions, including an instruction to enter a virtual machine. The control logic is to determine, in response to a privileged event occurring within the virtual machine, whether to generate a virtualization exception. The execution hardware is to generate a virtualization exception in response to the control logic determining to generate a virtualization exception.

Abstract: In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for implementing a balanced P-LRU tree for a “multiple of 3” number of ways cache. For example, in one embodiment, such means may include an integrated circuit having a cache and a plurality of ways. In such an embodiment the plurality of ways include a quantity that is a multiple of three and not a power of two, and further in which the plurality of ways are organized into a plurality of pairs. In such an embodiment, means further include a single bit for each of the plurality of pairs, in which each single bit is to operate as an intermediate level decision node representing the associated pair of ways and a root level decision node having exactly two individual bits to point to one of the single bits to operate as the intermediate level decision nodes representing an associated pair of ways.

Abstract: A method is described that includes performing the following for a transactional operation in response to a request from a processing unit that is directed to a cache identifying a cache line. Reading the cache line, and, if the cache line is in a Modified cache coherency protocol state, forwarding the cache line to circuitry that will cause the cache line to be written to deeper storage, and, changing another instance of the cache line that is available to the processing unit for the transactional operation to an Exclusive cache coherency state.

Abstract: The present invention comprises a combination of an eye tracking capable camera module coupled with one or more targets displayed on a screen. The most preferred embodiments of the present invention will track eye movement relative to the position of the targets displayed on the screen and authenticate a user based on a pre-determined visual movement pattern of the user's eye and the targets displayed on the screen. The pre-determined movement pattern may include eye movement patterns including directional movement, dwell time, delays, and other similar variations. Additionally, a method for authenticating a user by implementing a system that is capable of tracking and recording a user's eye movements is also disclosed.

Abstract: Embodiments of an invention for virtualization exceptions are disclosed. In one embodiment, a processor includes instruction hardware, control logic, and execution hardware. The instruction hardware is to receive a plurality of instructions, including an instruction to enter a virtual machine. The control logic is to determine, in response to a privileged event occurring within the virtual machine, whether to generate a virtualization exception. The execution hardware is to generate a virtualization exception in response to the control logic determining to generate a virtualization exception.

Abstract: In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for implementing a balanced P-LRU tree for a “multiple of 3” number of ways cache. For example, in one embodiment, such means may include an integrated circuit having a cache and a plurality of ways. In such an embodiment the plurality of ways include a quantity that is a multiple of three and not a power of two, and further in which the plurality of ways are organized into a plurality of pairs. In such an embodiment, means further include a single bit for each of the plurality of pairs, in which each single bit is to operate as an intermediate level decision node representing the associated pair of ways and a root level decision node having exactly two individual bits to point to one of the single bits to operate as the intermediate level decision nodes representing an associated pair of ways.

Abstract: A method is described that includes performing the following for a transactional operation in response to a request from a processing unit that is directed to a cache identifying a cache line.

Abstract: A miter attachment for use with a portable electric circular saw. This miter attachment has a smooth upper platform secured to rails positioned at 90.degree., and at 45.degree. right and left which are also secured to the base. A portable saw is placed on the upper platform with the circular blade in the marked pre-cut saw groove for true miter cutting. The saw shoe is fixed in position by clamps and the user releases the elevation knob on the saw, allowing it to move freely up and down on a pin hinged to the saw shoe. A plunge cut is achieved as the saw is lowered and the blade passes through the workpiece, placed and held against the rail between the upper platform and the base.