Abstract: The present application relates to an improved static random access memory (SRAM) device having a plurality of storage cells and a separate read/write circuit. Each of the plurality of storage cells is connected to a read/write data node of the read/write circuit by a dedicated connection, and an access switch which permits read/write access to the storage cell. The dedicated connection exhibits a greater capacitance than the read/write data node of the read/write circuit, such that the primary read mechanism of the SRAM is charge equalization. The SRAM write data connection to the read/write node of the read/write circuit, to permit data to be written to the plurality of storage cells. Write assist techniques are disclosed which assist writing of a ‘1’ to the plurality of storage cells.

Abstract: The present application relates to an improved static random access memory (SRAM) device having a plurality of storage cells and a separate read/write circuit. Each of the plurality of storage cells is connected to a read/write data node of the read/write circuit by a dedicated connection, and an access switch which permits read/write access to the storage cell. The dedicated connection exhibits a greater capacitance than the read/write data node of the read/write circuit, such that the primary read mechanism of the SRAM is charge equalisation. The SRAM write data connection to the read/write node of the read/write circuit, to permit data to be written to the plurality of storage cells. Write assist techniques are disclosed which assist writing of a ‘1’ to the plurality of storage cells.

Abstract: A programmable logic circuit comprising a plurality of programmable logic elements and a plurality of programmable interconnect means, and memory means for storing the configuration of the logic elements and interconnect means, wherein said memory means is formed and arranged to store a multiplicity of different configurations for each said logic element.

Abstract: Disclosed is a cmos sram cell including two cross-coupled inverters, each having a pmos and an nmos transistor, a first signal line connected to the sources of each of the nmos transistors, a second signal line, parallel to the first signal line, and connected to the source of one of said pmos transistors, and a third signal line connected to the source of the other of said pmos transistors. The third signal line may be orthogonal to the first and second signal lines. Also disclosed is a cmos sram cell including two cross-coupled inverters, a pair of bitlines for writing data to the cell, and at least one further bitline for reading data from the cell.

Abstract: A programmable logic circuit comprising a plurality of programmable logic elements and a plurality of programmable interconnect means, and memory means for storing the configuration of the logic elements and interconnect means, wherein said memory means is formed and arranged to store a multiplicity of different configurations for each said logic element.