Patents by Inventor Robert Charles Dockerty

Robert Charles Dockerty has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6395991
    Abstract: Structure and method for reinforcing a solder column grid array attachment of a ceramic or the like substrate to a printed circuit board, the reinforcement providing support for a heat sink which is bonded or affixed by pressure to a structural element of the substrate. In one form, the invention involves the concurrent formation of materially larger solder columns along the perimeter of the substrate in conjunction with the array of thin electrically interconnecting solder columns on the substrate. The reinforcing and electrical signal columns are thereafter aligned and attached by solder reflow to a corresponding pattern of pads on the printed circuit board. The heat sink is thermally connected to a structural element of the substrate by bonding or mechanical compression. Stresses in the solder columns caused by heat sink compressive forces or vibration induced flexing are materially decreased without adding complex or unique manufacturing operations.
    Type: Grant
    Filed: July 29, 1996
    Date of Patent: May 28, 2002
    Assignee: International Business Machines Corporation
    Inventors: Robert Charles Dockerty, Ronald Maurice Fraga, Ciro Neal Ramirez, Sudipta Kumar Ray, Gordon Jay Robbins
  • Patent number: 6053394
    Abstract: Structure and method for reinforcing a solder column grid array attachment of a ceramic or the like substrate to a printed circuit board, the reinforcement providing support for a heat sink which is bonded or affixed by pressure to a structural element of the substrate. In one form, the invention involves the concurrent formation of materially larger solder columns along the perimeter of the substrate in conjunction with the array of thin electrically interconnecting solder columns on the substrate. The reinforcing and electrical signal columns are thereafter aligned and attached by solder reflow to a corresponding pattern of pads on the printed circuit board. The heat sink is thermally connected to a structural element of the substrate by bonding or mechanical compression. Stresses in the solder columns caused by heat sink compressive forces or vibration induced flexing are materially decreased without adding complex or unique manufacturing operations.
    Type: Grant
    Filed: January 13, 1998
    Date of Patent: April 25, 2000
    Assignee: International Business Machines Corporation
    Inventors: Robert Charles Dockerty, Ronald Maurice Fraga, Ciro Neal Ramirez, Sudipta Kumar Ray, Gordon Jay Robbins
  • Patent number: 5796169
    Abstract: Supporting structure for a ball grid array surface mounted integrated circuit device composed of support solder formed at selective corner locations on the ball grid array surface of the integrated circuit device. In one form, L-shaped patterns of high melting temperature solder are formed along the axes defined by the ball grid array and are characterized in that cross sections of the L-shaped pattern match that of the solder balls along one axis, and represent a continuum of solder between solder ball locations along the other axis. Support solder can be added where necessary to provide both structural reinforcement and thermal conduction. Control of the cross section of the support solder ensures that surface tension effects of the molten low temperature reflow solder used to connect the integrated circuit device does not materially change the final relative spacing between the integrated circuit device balls and the underlying printed circuit board contacts.
    Type: Grant
    Filed: November 19, 1996
    Date of Patent: August 18, 1998
    Assignee: International Business Machines Corporation
    Inventors: Robert Charles Dockerty, Ronald Maurice Fraga, Ciro Neal Ramirez, Sudipta Kumar Ray, Charles Levern Reynolds, Jr., Gordon Jay Robbins
  • Patent number: 4062040
    Abstract: An improved field effect transistor structure which reduces a leakage phenomenon, termed the "sidewalk" effect, between the semiconductor substrate and a conductive silicon dioxide layer disposed over the substrate. The improvement comprises forming a layer of highly resistive, silicon dioxide or silicon oxynitride, which is between the conductive oxide and the silicon nitride layer which forms a portion of the gate insulator for the field effect transistor.
    Type: Grant
    Filed: March 24, 1977
    Date of Patent: December 6, 1977
    Assignee: IBM Corporation
    Inventors: Shakir Ahmed Abbas, Robert Charles Dockerty
  • Patent number: 4051273
    Abstract: An improved field effect transistor structure which reduces a leakage phenomenon, termed the "sidewalk" effect, between the semiconductor substrate and a conductive silicon dioxide layer disposed over the substrate. The improvement comprises forming a layer of highly resistive silicon dioxide or silicon oxynitride, which is between the conductive oxide and the silicon nitride layer which forms a portion of the gate insulator for the field effect transistor.
    Type: Grant
    Filed: November 26, 1975
    Date of Patent: September 27, 1977
    Assignee: IBM Corporation
    Inventors: Shakir Ahmed Abbas, Robert Charles Dockerty
  • Patent number: 4044452
    Abstract: A process and the resulting structure for making metal oxide silicon field effect transistors and vertical bipolar transistors on the same semiconductor chip with the devices being dielectrically isolated from each other. The process does not require an epitaxial layer. The bipolar devices have utility as cross-chip or off-chip drivers or can be utilized for analog circuitry.
    Type: Grant
    Filed: October 6, 1976
    Date of Patent: August 30, 1977
    Assignee: International Business Machines Corporation
    Inventors: Shakir Ahmed Abbas, Robert Charles Dockerty
  • Patent number: 4010482
    Abstract: A non-volatile memory cell that includes a Schottky barrier diode, located over a sub-diffused line or region formed within the substrate, acting as the control element. Information is stored in the device by introducing electrons into a nitride-oxide interface located at the perimeter of the Schottky barrier junction. Thus, the injected electrons are subject to trapping in the nitride-oxide layer, causing depletion in the epi region adjoining the diode interface, thereby influencing the current carrying state of the device.
    Type: Grant
    Filed: December 31, 1975
    Date of Patent: March 1, 1977
    Assignee: International Business Machines Corporation
    Inventors: Shakir Ahmed Abbas, Narasipur Gundappa Anantha, Robert Charles Dockerty