Patents by Inventor Robert Charles Dry
Robert Charles Dry has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230298958Abstract: The present disclosure relates to a package architecture and a method for making the same. The disclosed package architecture includes a package carrier, a first device die and a second device die mounted on the package carrier, and a heat spreader. The first device die includes a first device body with a thickness between 5 µm and 130 µm, a die carrier, and an attachment section between the first device body and the die carrier, while the second device die includes a second device body. The first device body and the second device body are formed of different materials. A top surface of the die carrier of the first device die and a top surface of the second device body of the second device die are substantially coplanar. The heat spreader resides over the top surface of the die carrier and the top surface of the second device body.Type: ApplicationFiled: April 19, 2023Publication date: September 21, 2023Inventors: Anthony Chiu, Robert Charles Dry, Mihir Roy
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Patent number: 11637050Abstract: The present disclosure relates to a package architecture and a method for making the same. The disclosed package architecture includes a package carrier, a first device die and a second device die mounted on the package carrier, and a heat spreader. The first device die includes a first device body with a thickness between 5 ?m and 130 ?m, a die carrier, and an attachment section between the first device body and the die carrier, while the second device die includes a second device body. The first device body and the second device body are formed of different materials. A top surface of the die carrier of the first device die and a top surface of the second device body of the second device die are substantially coplanar. The heat spreader resides over the top surface of the die carrier and the top surface of the second device body.Type: GrantFiled: March 31, 2021Date of Patent: April 25, 2023Assignee: Qorvo US, Inc.Inventors: Anthony Chiu, Robert Charles Dry, Mihir Roy
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Publication number: 20220319945Abstract: The present disclosure relates to a package architecture and a method for making the same. The disclosed package architecture includes a package carrier, a first device die and a second device die mounted on the package carrier, and a heat spreader. The first device die includes a first device body with a thickness between 5 ?m and 130 ?m, a die carrier, and an attachment section between the first device body and the die carrier, while the second device die includes a second device body. The first device body and the second device body are formed of different materials. A top surface of the die carrier of the first device die and a top surface of the second device body of the second device die are substantially coplanar. The heat spreader resides over the top surface of the die carrier and the top surface of the second device body.Type: ApplicationFiled: March 31, 2021Publication date: October 6, 2022Inventors: Anthony Chiu, Robert Charles Dry, Mihir Roy
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Patent number: 11244884Abstract: The present disclosure relates to a semiconductor package, which includes a carrier, a flip-chip die, a mold compound, and a heat spreader. Herein, the flip-chip die includes a device layer over the carrier and a die substrate over the device layer. The mold compound resides over the carrier and surrounds the flip-chip die. The mold compound has a recess adjacent to the flip-chip die, and the recess extends vertically lower than a top surface of the die substrate. The heat spreader hangs over the flip-chip die, and includes a spreader body that is thermally coupled to the die substrate, and a spreader protrusion that extends from the spreader body into the recess. A thickness of the spreader protrusion is shorter than a depth of the recess, and a width of the spreader protrusion is narrower than a width of the recess, such that the spreader protrusion is floating in the recess.Type: GrantFiled: July 10, 2020Date of Patent: February 8, 2022Assignee: Qorvo US, Inc.Inventor: Robert Charles Dry
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Patent number: 11114363Abstract: Electronic package arrangements and related methods are disclosed that provide one or more of improved thermal management and electromagnetic shielding. Electronic packages are disclosed that include arrangements of one or more electronic devices, overmold bodies, and heat spreaders or metal frame structures. The heat spreaders or metal frame structures may be arranged over the electronic devices to form heat dissipation paths that draw operating heat away from the electronic devices in one or more directions including above and below the electronic packages. The heat spreaders or metal frame structures may also be arranged to form electromagnetic shields that reduce crosstalk between the electronic devices within the electronic packages and to suppress unwanted emissions from either escaping or entering the electronic packages.Type: GrantFiled: September 23, 2019Date of Patent: September 7, 2021Assignee: Qorvo US, Inc.Inventors: Deepukumar M. Nair, Robert Charles Dry, Jeffrey Dekosky
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Patent number: 10872837Abstract: The present disclosure relates to an air-cavity semiconductor package, which includes a thermal carrier, a ring structure, a package lid, and at least one semiconductor device. The thermal carrier has a carrier body, a heat slug residing within the carrier body, a top coating layer formed over a top surface of the heat slug, and a bottom coating layer formed over a bottom surface of the heat slug. The ring structure includes a ring body with an interior opening, which resides over the thermal carrier, such that a portion of a top surface of the thermal carrier is exposed through the interior opening. The package lid resides over the ring structure and has a recess conjoined with the interior opening forming an enclosed cavity. The at least one semiconductor device is attached to the exposed portion of the top surface of the thermal carrier and encapsulated in the enclosed cavity.Type: GrantFiled: May 8, 2019Date of Patent: December 22, 2020Assignee: Qorvo US, Inc.Inventors: Robert Charles Dry, Christine Blair
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Patent number: 10855240Abstract: Improved structures for spatial power-combining devices are disclosed. A spatial power-combining device includes a plurality of amplifier assemblies and each amplifier assembly includes a body structure that supports an input antenna structure, an amplifier, and an output antenna structure. According to embodiments disclosed herein, the body structure comprises a material that is configured to provide the spatial power-combining device with reduced weight while maintaining good thermal dissipation for heat generated by the amplifiers. In certain embodiments, the body structure may comprise an allotrope of carbon such as graphite or graphene, among others. In certain embodiments, the body structure may include one or more thermal vias configured to dissipate heat from the amplifier.Type: GrantFiled: November 15, 2018Date of Patent: December 1, 2020Assignee: Qorvo US, Inc.Inventors: Christo Bojkov, Dylan Murdock, Robert Charles Dry
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Publication number: 20200357716Abstract: The present disclosure relates to an air-cavity semiconductor package, which includes a thermal carrier, a ring structure, a package lid, and at least one semiconductor device. The thermal carrier has a carrier body, a heat slug residing within the carrier body, a top coating layer formed over a top surface of the heat slug, and a bottom coating layer formed over a bottom surface of the heat slug. The ring structure includes a ring body with an interior opening, which resides over the thermal carrier, such that a portion of a top surface of the thermal carrier is exposed through the interior opening. The package lid resides over the ring structure and has a recess conjoined with the interior opening forming an enclosed cavity. The at least one semiconductor device is attached to the exposed portion of the top surface of the thermal carrier and encapsulated in the enclosed cavity.Type: ApplicationFiled: May 8, 2019Publication date: November 12, 2020Inventors: Robert Charles Dry, Christine Blair
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Patent number: 10832984Abstract: A method includes the steps of fabricating one or more semiconductor devices on a semiconductor wafer and depositing one or more conformal organic environmental protection layers over the semiconductor wafer using a vapor deposition process. By depositing the one or more conformal organic environmental protection layers using a vapor deposition process, thin film conformal organic environmental protection layers may be provided that offer excellent protection against water and oxygen ingress, thus increasing the ruggedness and reliability of the resulting semiconductor die.Type: GrantFiled: January 15, 2020Date of Patent: November 10, 2020Assignee: Qorvo US, Inc.Inventors: Christo Bojkov, Andrew Ketterson, Robert Charles Dry
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Publication number: 20200343157Abstract: The present disclosure relates to a semiconductor package, which includes a carrier, a flip-chip die, a mold compound, and a heat spreader. Herein, the flip-chip die includes a device layer over the carrier and a die substrate over the device layer. The mold compound resides over the carrier and surrounds the flip-chip die. The mold compound has a recess adjacent to the flip-chip die, and the recess extends vertically lower than a top surface of the die substrate. The heat spreader hangs over the flip-chip die, and includes a spreader body that is thermally coupled to the die substrate, and a spreader protrusion that extends from the spreader body into the recess. A thickness of the spreader protrusion is shorter than a depth of the recess, and a width of the spreader protrusion is narrower than a width of the recess, such that the spreader protrusion is floating in the recess.Type: ApplicationFiled: July 10, 2020Publication date: October 29, 2020Inventor: Robert Charles Dry
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Patent number: 10734301Abstract: The present disclosure relates to a semiconductor package, which includes a carrier, a flip-chip die, a mold compound, and a heat spreader. Herein, the flip-chip die includes a device layer over the carrier and a die substrate over the device layer. The mold compound resides over the carrier and surrounds the flip-chip die. The mold compound has a recess adjacent to the flip-chip die, and the recess extends vertically lower than a top surface of the die substrate. The heat spreader hangs over the flip-chip die, and includes a spreader body that is thermally coupled to the die substrate, and a spreader protrusion that extends from the spreader body into the recess. A thickness of the spreader protrusion is shorter than a depth of the recess, and a width of the spreader protrusion is narrower than a width of the recess, such that the spreader protrusion is floating in the recess.Type: GrantFiled: February 21, 2019Date of Patent: August 4, 2020Assignee: Qorvo US, Inc.Inventor: Robert Charles Dry
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Publication number: 20200203248Abstract: Electronic package arrangements and related methods are disclosed that provide one or more of improved thermal management and electromagnetic shielding. Electronic packages are disclosed that include arrangements of one or more electronic devices, overmold bodies, and heat spreaders or metal frame structures. The heat spreaders or metal frame structures may be arranged over the electronic devices to form heat dissipation paths that draw operating heat away from the electronic devices in one or more directions including above and below the electronic packages. The heat spreaders or metal frame structures may also be arranged to form electromagnetic shields that reduce crosstalk between the electronic devices within the electronic packages and to suppress unwanted emissions from either escaping or entering the electronic packages.Type: ApplicationFiled: September 23, 2019Publication date: June 25, 2020Inventors: Deepukumar M. Nair, Robert Charles Dry, Jeffrey Dekosky
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Publication number: 20200162046Abstract: Improved structures for spatial power-combining devices are disclosed. A spatial power-combining device includes a plurality of amplifier assemblies and each amplifier assembly includes a body structure that supports an input antenna structure, an amplifier, and an output antenna structure. According to embodiments disclosed herein, the body structure comprises a material that is configured to provide the spatial power-combining device with reduced weight while maintaining good thermal dissipation for heat generated by the amplifiers. In certain embodiments, the body structure may comprise an allotrope of carbon such as graphite or graphene, among others. In certain embodiments, the body structure may include one or more thermal vias configured to dissipate heat from the amplifier.Type: ApplicationFiled: November 15, 2018Publication date: May 21, 2020Inventors: Christo Bojkov, Dylan Murdock, Robert Charles Dry
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Publication number: 20200152533Abstract: A method includes the steps of fabricating one or more semiconductor devices on a semiconductor wafer and depositing one or more conformal organic environmental protection layers over the semiconductor wafer using a vapor deposition process. By depositing the one or more conformal organic environmental protection layers using a vapor deposition process, thin film conformal organic environmental protection layers may be provided that offer excellent protection against water and oxygen ingress, thus increasing the ruggedness and reliability of the resulting semiconductor die.Type: ApplicationFiled: January 15, 2020Publication date: May 14, 2020Inventors: Christo Bojkov, Andrew Ketterson, Robert Charles Dry
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Patent number: 10651103Abstract: A method includes the steps of fabricating one or more semiconductor devices on a semiconductor wafer and depositing one or more conformal organic environmental protection layers over the semiconductor wafer using a vapor deposition process. By depositing the one or more conformal organic environmental protection layers using a vapor deposition process, thin film conformal organic environmental protection layers may be provided that offer excellent protection against water and oxygen ingress, thus increasing the ruggedness and reliability of the resulting semiconductor die.Type: GrantFiled: October 30, 2017Date of Patent: May 12, 2020Assignee: Qorvo US, Inc.Inventors: Christo Bojkov, Andrew Ketterson, Robert Charles Dry
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Patent number: 10615091Abstract: A method includes the steps of fabricating one or more semiconductor devices on a semiconductor wafer and depositing one or more conformal organic environmental protection layers over the semiconductor wafer using a vapor deposition process. By depositing the one or more conformal organic environmental protection layers using a vapor deposition process, thin film conformal organic environmental protection layers may be provided that offer excellent protection against water and oxygen ingress, thus increasing the ruggedness and reliability of the resulting semiconductor die.Type: GrantFiled: October 30, 2017Date of Patent: April 7, 2020Assignee: Qorvo US, Inc.Inventors: Christo Bojkov, Andrew Ketterson, Robert Charles Dry
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Publication number: 20200083136Abstract: The present disclosure relates to a semiconductor package, which includes a carrier, a flip-chip die, a mold compound, and a heat spreader. Herein, the flip-chip die includes a device layer over the carrier and a die substrate over the device layer. The mold compound resides over the carrier and surrounds the flip-chip die. The mold compound has a recess adjacent to the flip-chip die, and the recess extends vertically lower than a top surface of the die substrate. The heat spreader hangs over the flip-chip die, and includes a spreader body that is thermally coupled to the die substrate, and a spreader protrusion that extends from the spreader body into the recess. A thickness of the spreader protrusion is shorter than a depth of the recess, and a width of the spreader protrusion is narrower than a width of the recess, such that the spreader protrusion is floating in the recess.Type: ApplicationFiled: February 21, 2019Publication date: March 12, 2020Inventor: Robert Charles Dry
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Patent number: 10199313Abstract: The present disclosure relates to a ring-frame power package that includes a thermal carrier, a spacer ring residing on the thermal carrier, and a ring structure residing on the spacer ring. The ring structure includes a ring body and a number of interconnect tabs that protrude from an outer periphery of the ring body. Herein, a portion of the carrier surface of the thermal carrier is exposed through an interior opening of the spacer ring and an interior opening of the ring body. The spacer ring is not electronically conductive and prevents the interconnect tabs from electrically coupling to the thermal carrier. Each interconnect tab includes a top plated area and a bottom plated area, which is electrically coupled to the top plated area.Type: GrantFiled: August 1, 2017Date of Patent: February 5, 2019Assignee: Qorvo US, Inc.Inventor: Robert Charles Dry
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Patent number: 10008473Abstract: The present disclosure relates to a ring-frame power package. In this regard, the ring-frame power package includes a thermal carrier and a ring structure. The thermal carrier has a carrier surface. The ring structure includes a ring body that is disposed over the carrier surface of the thermal carrier so that a portion of the carrier surface is exposed through an interior opening of the ring body. The ring-frame power package also includes a power package lid that is disposed over the ring body. The power package lid includes a cavity in communication with the interior opening of the ring body. In this manner, the power package lid covers and protects semiconductor devices and corresponding wires encased by the ring-frame power package.Type: GrantFiled: April 28, 2016Date of Patent: June 26, 2018Assignee: Qorvo US, Inc.Inventors: Robert Charles Dry, Steve Jones, Jonathan Fain
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Publication number: 20180122716Abstract: A method includes the steps of fabricating one or more semiconductor devices on a semiconductor wafer and depositing one or more conformal organic environmental protection layers over the semiconductor wafer using a vapor deposition process. By depositing the one or more conformal organic environmental protection layers using a vapor deposition process, thin film conformal organic environmental protection layers may be provided that offer excellent protection against water and oxygen ingress, thus increasing the ruggedness and reliability of the resulting semiconductor die.Type: ApplicationFiled: October 30, 2017Publication date: May 3, 2018Inventors: Christo Bojkov, Andrew Ketterson, Robert Charles Dry