Abstract: An apparatus and method are disclosed for converting digital input signals of either polarity to representative analog output signals. An internal synchronous counter is clocked to generate internal digital signals of the same code as the input digital signal which are compared with the input digital signal which is stored in a bank of latches. Upon coincidence therebetween, an inhibiting pulse is produced from a coincidence circuit for disabling a buffer-integrator circuit. During the time interval between the enabling of the counter and the inhibiting pulse, the buffer-integrator integrates a single polarity reference voltage provided thereto to establish an analog voltage representative of the stored digital signal. Sample and hold circuits periodically sample the output of the integrator circuit to update and provide the analog output. Self compensation for operational amplifier offsets is provided during each conversion cycle.

Abstract: A linear voltage amplifier includes an input stage which has a P channel MOSFET load device and an N channel input device. The complementary amplifier also includes a feedback circuit which includes a low pass filter coupled between the output stage and the gate electrode of the P channel load device. The P type tub region in which the N channel input MOSFET is located is biased by an adjustable bias circuit to control threshold voltage of the input MOSFET and thereby control the DC level of the output of the complementary amplifier. In one embodiment the biasing circuit includes a P channel MOSFET coupled in series with a diode connected N channel MOSFET between two voltage supply conductors, the gate of the P channel MOSFET being connected to the gate of the P channel MOSFET load device of the input stage.

Abstract: An electronic circuit suitable to be fabricated in monolithic integrated circuit form for producing at an output terminal an output signal for a predetermined time period of which the value thereof corresponds to the value of a periodically sampled, time varying, input signal applied at an input terminal. The circuit comprises two identical and parallel channels connected between the input and the output terminals such that one channel is in a sample mode while the other channel is in a hold mode and vice versa. Each channel includes a pair of operational amplifiers operatively coupled to an integrating capacitor. The dual channel system provides self compensation for offset voltage and common mode rejection. Thus, no manual nulling adjustment is required. Because self compensation is renewed each sample/hold cycle, the circuit is substantially insensitive to temperature variations over a broad range of temperatures.