Abstract: In an embodiment, a method of operating a memory cell coupled to a first port and to a second port includes determining if a first port is requesting to access the memory cell and determining if a second port is requesting to access the memory cell. Based on the determining, if the first port and the second port are simultaneously requesting to access the memory cell, the second port is deactivated, the memory cell is accessed from the first port, and an accessed memory state is propagated from the first port to circuitry associated with the second port.

Abstract: In an embodiment, a method of operating a memory cell coupled to a first port and to a second port includes determining if a first port is requesting to access the memory cell and determining if a second port is requesting to access the memory cell. Based on the determining, if the first port and the second port are simultaneously requesting to access the memory cell, the second port is deactivated, the memory cell is accessed from the first port, and an accessed memory state is propagated from the first port to circuitry associated with the second port.

Abstract: An SRAM having asymmetrical FET pass gates and a method of fabricating an SRAM having asymmetrical FET pass gates. The pass gates are asymmetrical with respect to current conduction from the drain to the source of the pass gate being different from current conduction from the source to the drain of the pass gate.

Abstract: An SRAM having asymmetrical FET pass gates and a method of fabricating an SRAM having asymmetrical FET pass gates. The pass gates are asymmetrical with respect to current conduction from the drain to the source of the pass gate being different from current conduction from the source to the drain of the pass gate.

Abstract: A method and system for mitigating the impact of radiation induced in a data processor incorporating integrated circuits. The method comprises the steps of determining the location of the data processor, determining a set of radiation sources and intensities at that location, and estimating the soft error rate of the data processor as a function of the determined radiation intensities and geometric characteristics of said integrated circuits to provide an estimate value. The data processor is modified (either hardware or software) in response to the estimate value at times the estimate value exceeds a predetermined value.

Abstract: Methods for designing a 6T SRAM cell having greater stability and/or a smaller cell size are provided. A 6T SRAM cell has a pair access transistors (NFETs), a pair of pull-up transistors (PFETs), and a pair of pull-down transistors (NFETs), wherein the access transistors have a higher threshold voltage than the pull-down transistors, which enables the SRAM cell to effectively maintain a logic “0” during access of the cell thereby increasing the stability of the cell, especially for cells during “half select.” Further, a channel width of a pull-down transistor can be reduced thereby decreasing the size of a high performance six transistor SRAM cell without effecting cell the stability during access. And, by decreasing the cell size, the overall design layout of a chip may also be decreased.

Abstract: A method and system for mitigating the impact of radiation induced in a data processor incorporating integrated circuits. The method comprises the steps of determining the location of the data processor, determining a set of radiation sources and intensities at that location, and estimating the soft error rate of the data processor as a function of the determined radiation intensities and geometric characteristics of said integrated circuits to provide an estimate value. The data processor is modified (either hardware or software) in response to the estimate value at times the estimate value exceeds a predetermined value.

Abstract: An improved storage system for use with computers. The system includes a memory array bifurcated into a first and second array segment and a differential sense amplifier configured for selective operation in a first mode establishing one array segment as a reference load and the other array segment as a dynamic load, and a second mode establishing the other array segment as a reference load and the one array segment as a dynamic load. The amplifier senses changes in a parameter in the dynamic load with respect to the reference load.

Abstract: An improved differential sense amplifier for sensing differences in a parameter at a first locus coupled with a first signal source and a second locus coupled with a second signal source. The sensing is effected by a first sensing element coupled with the first locus and a second sensing element coupled with the second locus. The improvement comprises the first sensing element and the second sensing element having differing sensitivities. In the preferred embodiment of the invention, the sensing elements are field effect transistors, and the sensitivity is established by a threshold voltage characteristic. Preferably, the first signal source provides a dynamic signal to be measured and the second signal source provides a reference signal against which the dynamic signal's changes are compared.