Patents by Inventor Robert Chin Fu Tsai

Robert Chin Fu Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080182179
    Abstract: A gray tone mask includes a transparent substrate and a light blocking layer. The light blocking layer is disposed on the transparent substrate and has a transparent region with a minimum thickness, an opaque region with a maximum thickness and a gray tone region with an intermediate thickness, wherein the intermediate thickness is between the minimum thickness and the maximum thickness, and the optical transmissivity of the gray tone region is approximately between 5% and 95%.
    Type: Application
    Filed: January 25, 2007
    Publication date: July 31, 2008
    Applicant: ALLIED INTEGRATED PATTERNING CORP.
    Inventor: Robert Chin Fu TSAI
  • Patent number: 7052372
    Abstract: A polish apparatus for planarizing wafers and films over wafers comprising the following. A substrate chuck for holding a substrate with a surface to be polished thereof being directed about vertically. A first drive means for rotating the substrate chuck. A polishing head having a polishing surface which is adjacent to the substrate during the polishing of the substrate. The polishing surface of the polishing head is smaller than the surface of the substrate. A polishing solution supply means for supplying a polishing solution through the polishing head to the substrate held by the substrate chuck. A reciprocating means for reciprocally moving the polishing head on the surface to be polished. A pressing means for pressing the polishing pad against a substrate held by the substrate chuck by way of the polishing head. The polish head is preferably comprised of one piece of molded polymer. No polish pad is used.
    Type: Grant
    Filed: December 13, 2001
    Date of Patent: May 30, 2006
    Assignee: Chartered Semiconductor Manufacturing, LTD
    Inventors: Seng-Keong Victor Lim, Paul Richard Proctor, Robert Chin Fu Tsai
  • Publication number: 20030114086
    Abstract: A polish apparatus for planarizing wafers and films over wafers comprising the following. A substrate chuck for holding a substrate with a surface to be polished thereof being directed about vertically. A first drive means for rotating the substrate chuck. A polishing head having a polishing surface which is adjacent to the substrate during the polishing of the substrate. The polishing surface of the polishing head is smaller than the surface of the substrate. A polishing solution supply means for supplying a polishing solution through the polishing head to the substrate held by the substrate chuck. A reciprocating means for reciprocally moving the polishing head on the surface to be polished. A pressing means for pressing the polishing pad against a substrate held by the substrate chuck by way of the polishing head. The polish head is preferably comprised of one piece of molded polymer. No polish pad is used.
    Type: Application
    Filed: December 13, 2001
    Publication date: June 19, 2003
    Inventors: Seng-Keong Victor Lim, Paul Richard Proctor, Robert Chin Fu Tsai
  • Patent number: 6180430
    Abstract: A method of fabricating an LCD-on-silicon device, comprising the following steps. A semiconductor structure having a control transistor formed therein is provided. The control transistor having a source and a drain. An interlevel dielectric (ILD) layer over the semiconductor structure is provided. Source/drain (S/D) plugs contacting the source and drain through contact openings in said ILD layer are provided. M1 lines are formed over the ILD layer and connected to at least the S/D plugs. An M1 intermetal dielectric (IMD) layer is deposited and patterned over the M1 lines to form M1 contact openings exposing at least some of the M1 metal lines. M1 metal plugs are formed within the M1 contact openings and M2 metal islands connected to, and integral with, at least the M1 metal plugs. The M2 metal islands having exposed side walls. Sidewall spacers are formed on the exposed M2 metal islands side walls.
    Type: Grant
    Filed: December 13, 1999
    Date of Patent: January 30, 2001
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Sik On Kong, Dai Feng, Yung-Tao Lin, Robert Chin Fu Tsai