Abstract: The present invention relates functional ligands to target molecules, particularly to functional nucleic acids and modifications thereof, and to methods for simultaneously generating, for example, numerous different functional biomolecules, particularly to methods for generating numerous different functional nucleic acids against multiple target molecules simultaneously. The present invention further relates to functional ligands which bind with affinity to target molecules.

Abstract: An electrically conductive interconnect is provided through an opening in a dielectric layer, electrically connecting two conductive layers. In one embodiment, the interconnect is formed by ruthenium entirely filling the opening in the dielectric layer. In another embodiment, an adhesion layer of titanium is provided in the opening prior to providing the ruthenium. In using this approach, an aspect ratio (i.e., the ratio of the length of the interconnect to the width thereof) of 20:1 or greater is achievable.

Abstract: An integrated circuit includes first and second voltage domains. The first voltage domain is associated with a positive voltage supply grid and the second voltage domain is associated with a selectably on voltage supply grid. A switch is used to selectably switch on and off the selectably on voltage supply grid to power the second voltage domain. A buffer cell cluster of at least on initial buffer cell and a pair of insulator cells is coupled to the positive voltage supply grid electrically independent of the nodes of a switch and is capable of buffering a feed-through signal having a logic one voltage level defined substantially at the voltage level of the positive voltage supply grid. The buffer cell cluster has two distal ends. buffer cell cluster, at one distal end, is coupled to a first insulator cell of the pair of cells while, at the other distal end, the buffer cell cluster is coupled to a second insulator cell of the pair of the cells.

Abstract: An electrically conductive interconnect is provided through an opening in a dielectric layer, electrically connecting two conductive layers. In one embodiment, the interconnect is formed by ruthenium entirely filling the opening in the dielectric layer. In another embodiment, an adhesion layer of titanium is provided in the opening prior to providing the ruthenium. In using this approach, an aspect ratio (i.e., the ratio of the length of the interconnect to the width thereof) of 20:1 or greater is achievable.

Abstract: In fabricating an electronic structure, a substrate is provided, and a first barrier layer is provided on the substrate. A germanium thin film diode is provided on the first barrier layer, and a second barrier layer is provided on the germanium thin film diode. A memory device is provided over and connected to the second barrier layer.

Abstract: The present invention provides nucleic acids that include a nucleotide sequence that encodes an siRNA, which nucleotide sequence is operably linked to a target cell-specific promoter RNA polymerase II promoter. The present invention further provides vectors, including expression vectors, which include a subject nucleic acid; and host cells that harbor a subject nucleic acid or a subject expression vector. The present invention further provides methods of modulating (e.g., reducing) expression of a gene in a target cell-specific manner, the methods generally involving introducing into a cell a subject expression vector.

Abstract: A method for manufacturing a memory device having a metal nanocrystal charge storage structure. A substrate is provided and a first layer of dielectric material is grown on the substrate. A layer of metal oxide having a first heat of formation is formed on the first layer of dielectric material. A metal layer having a second heat of formation is formed on the metal oxide layer. The second heat of formation is greater than the first heat of formation. The metal oxide layer and the metal layer are annealed which causes the metal layer to reduce the metal oxide layer to metallic form, which then agglomerates to form metal islands. The metal layer becomes oxidized thereby embedding the metal islands within an oxide layer to form a nanocrystal layer. A control oxide is formed over the nanocrystal layer and a gate electrode is formed on the control oxide.

Abstract: An integrated circuit is provided. A gate dielectric is formed on a semiconductor substrate, and a gate is formed over the gate dielectric. A sidewall spacer is formed around the gate and a source/drain junction is formed in the semiconductor substrate using the sidewall spacer. A bottom silicide metal is deposited on the source/drain junction and then a top silicide metal is deposited on the bottom silicide metal. The bottom and top silicide metals are formed into their suicides. A dielectric layer is deposited above the semiconductor substrate and a contact is formed in the dielectric layer to the top silicide.

Abstract: A structure of an integrated circuit is provided. A gate dielectric is formed on a semiconductor substrate, and a gate is formed over a gate dielectric on the semiconductor substrate. Source/drain junctions are formed in the semiconductor substrate. Ultra-uniform suicides are formed on the source/drain junctions, and a dielectric layer is deposited above the semiconductor substrate. Contacts are then formed in the dielectric layer to the ultra-uniform silicides.

Abstract: A method of forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. Source/drain junctions are formed in the semiconductor substrate. A sidewall spacer is formed around the gate using a low power plasma enhanced chemical vapor deposition process A silicide is formed on the source/drain junctions and on the gate, and an interlayer dielectric is deposited above the semiconductor substrate. Contacts are then formed in the interlayer dielectric to the silicide.

Abstract: A method of forming and a structure of an integrated circuit are provided. A gate dielectric is formed on a semiconductor substrate, and a gate is formed over a gate dielectric on the semiconductor substrate. Source/drain junctions are formed in the semiconductor substrate. Ultra-uniform silicides are formed on the source/drain junctions, and a dielectric layer is deposited above the semiconductor substrate. Contacts are then formed in the dielectric layer to the ultra-uniform silicides.

Abstract: A range hood includes a motor housing having two slanted motor supporting platforms provided thereon wherein two motor are detachably mounted on the two slanted motor supporting platforms respectively such that the motors are inclined with respect to a ceiling of a casing. A drag area provided by the inclined motor arrangement is highly increased in order cover the entire cooking surface. Furthermore, all parts of the range hood are adapted to be assembled and disassembled without using tools such that a user is able to easily clean up the range hood part by part in which the parts made of durable material are dishwasher-safe so as to easily maintain the range hood for better performance.