Abstract: Various implementations described herein are related to a device having adaptive clocking architecture with multiple stages of latches and buffers coupled in a delay line configuration. In some instances, each latch receives a delayed clock signal as data input and provides a sample out signal as a latched output based on a clock signal. Also, in some instances, each latch provides a delayed edge of a next clock cycle so as to stretch the pulse width of the clock signal.

Abstract: Various implementations described herein are directed to a device having a set-reset architecture with multiple latches including a first latch, a second latch and a third latch. The first latch may receive a first data signal from first logic and provide a first latched data signal as a first output based on a clock signal. The second latch may receive a second data signal from second logic and provide a second latched data signal as a second output based on the clock signal. The third latch may receive a third data signal from third logic and provide a third latched data signal as a third output based on the clock signal.

Abstract: An apparatus is provided to enable power supply input to be isolated from power supply output. Power is received from a first power signal at a first of a plurality of charge stores. A second power signal is output from a second of the plurality of charge stores. The second power signal is isolated from the first power supply. The first charge store can be charged from the power input whilst isolated from the power output. The second charge store can be discharged to the power output, while isolated from the power input.

Abstract: Various implementations described herein are directed to device having multiple stages. The device may include a first stage that converts an analog voltage signal in a power supply domain into a digitally coded signal. The device may include a second stage that generates a derivative of the digitally coded signal, detects an event of the analog voltage signal based on the derivative of the digitally coded signal, and derives a control signal based on the event. The device may include a third stage that injects current into or sinks current from the power supply domain that is associated with the analog voltage signal based on the control signal.

Abstract: Power is received from a first power signal at a first of a plurality of charge stores. A second power signal is output from a second of the plurality of charge stores. The second power signal is isolated from the first power supply.