Patents by Inventor Robert Christopher Bowen

Robert Christopher Bowen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Device contact structures including heterojunctions for low contact resistance
    Patent number: 9917158
    Abstract: A semiconductor device can include a channel region with a first semiconductor material for a majority carrier in the channel region during operation (on state) of the device and a metal contact. A source/drain region can include a semiconductor material alloy including a second semiconductor material and at least one heterojunction located between the metal contact and the channel region, wherein the heterojunction forms a band-edge offset for the majority carrier that is less than or equal to about 0.2 eV.
    Type: Grant
    Filed: November 16, 2015
    Date of Patent: March 13, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jorge A. Kittl, Borna Josip Obradovic, Robert Christopher Bowen, Mark S. Rodder
  • Structure and method to achieve compressively strained Si NS
    Patent number: 9831323
    Abstract: A stack for a semiconductor device and a method for making the stack are disclosed. The stack includes a plurality of sacrificial layers in which each sacrificial layer has a first lattice parameter; and at least one channel layer that has a second lattice parameter in which the first lattice parameter is less than or equal to the second lattice parameter, and each channel layer is disposed between and in contact with two sacrificial layers and includes a compressive strain or a neutral strain based on a difference between the first lattice parameter and the second lattice parameter.
    Type: Grant
    Filed: September 15, 2016
    Date of Patent: November 28, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jorge A. Kittl, Ganesh Hegde, Robert Christopher Bowen, Borna J. Obradovic, Mark S. Rodder
  • STRUCTURE AND METHOD TO ACHIEVE COMPRESSIVELY STRAINED SI NS
    Publication number: 20170263728
    Abstract: A stack for a semiconductor device and a method for making the stack are disclosed. The stack includes a plurality of sacrificial layers in which each sacrificial layer has a first lattice parameter; and at least one channel layer that has a second lattice parameter in which the first lattice parameter is less than or equal to the second lattice parameter, and each channel layer is disposed between and in contact with two sacrificial layers and includes a compressive strain or a neutral strain based on a difference between the first lattice parameter and the second lattice parameter.
    Type: Application
    Filed: September 15, 2016
    Publication date: September 14, 2017
    Inventors: Jorge A. KITTL, Ganesh HEGDE, Robert Christopher BOWEN, Borna J. OBRADOVIC, Mark S. RODDER
  • DEVICE CONTACT STRUCTURES INCLUDING HETEROJUNCTIONS FOR LOW CONTACT RESISTANCE
    Publication number: 20160079372
    Abstract: A semiconductor device can include a channel region with a first semiconductor material for a majority carrier in the channel region during operation (on state) of the device and a metal contact. A source/drain region can include a semiconductor material alloy including a second semiconductor material and at least one heterojunction located between the metal contact and the channel region, wherein the heterojunction forms a band-edge offset for the majority carrier that is less than or equal to about 0.2 eV.
    Type: Application
    Filed: November 16, 2015
    Publication date: March 17, 2016
    Inventors: Jorge A. Kittl, Borna Josip Obradovic, Robert Christopher Bowen, Mark S. Rodder