Abstract: An integrated circuit includes queue circuits for storing packets, a scheduler circuit that schedules the packets received from the queue circuits to be provided in an output, and a traffic manager circuit that disables one of the queue circuits from transmitting any of the packets to the scheduler circuit based at least in part on a bandwidth in the output scheduled for a subset of the packets received from the one of the queue circuits.

Abstract: An apparatus for implementing a minimum toggle rate guarantee may comprise first, second, and third circuitries. The first circuitry may calculate a sequence of values for an internal bus inversion signal based upon a sequence of values for a plurality of internal Input/Output (IO) signals. The second circuitry may establish a sequence of values for an external bus inversion signal by selecting between the sequence of values for the internal bus inversion signal and a sequence of substantially random values. The third circuitry may set the values for a plurality of external IO signals to inverted values of the plurality of internal signals when respectively corresponding sequence of values for the external bus inversion signal have a first value, and to values of the plurality of internal signals when respectively corresponding sequence of values for the external bus inversion signal have a second value.

Abstract: An apparatus for implementing a minimum toggle rate guarantee may comprise first, second, and third circuitries. The first circuitry may calculate a sequence of values for an internal bus inversion signal based upon a sequence of values for a plurality of internal Input/Output (IO) signals. The second circuitry may establish a sequence of values for an external bus inversion signal by selecting between the sequence of values for the internal bus inversion signal and a sequence of substantially random values. The third circuitry may set the values for a plurality of external IO signals to inverted values of the plurality of internal signals when respectively corresponding sequence of values for the external bus inversion signal have a first value, and to values of the plurality of internal signals when respectively corresponding sequence of values for the external bus inversion signal have a second value.

Abstract: One embodiment relates to a method of communicating a data packet stream in which data is re-packed to reduce wasted bandwidth. Data bytes of the data packet stream are received from a first data path and mapped to a second data path that is divided into a plurality of data segments. At least one data byte is mapped to each data segment until an end of, or pause in, the data packet stream. Another embodiment relates to a method of communicating data packets from multiple channels. Multiple data packet flows, each flow corresponding to a channel, is received on a first data path. The data bytes from the first data path are mapped to a second data path that is divided into multiple data segments. At least one data byte is mapped to each data segment until an end of, or pause in, the multiple data packet flows. Other embodiments, aspects, and features of the invention are also disclosed.