Abstract: Touch sensors with one or more piezoelectric elements and devices containing such touch sensors are presented. The touch sensor contains keys that are independently actuated. Contact with a key provides tactile feedback through the piezoelectric element to the user. Each key provides an individual tactile feedback pattern that is dependent on the particular key contacted as well as the function of the key at the time of contact. Actuation of the key provides a different tactile feedback pattern. The piezoelectric element is bonded directly to a printed circuit board, on which electronic components are also mounted.

Abstract: Embedded capacitors comprise a bimetal foil (500) that includes a first copper layer (205) and an aluminum layer (210) on the first copper layer. The aluminum layer has a smooth side adjacent the first copper layer and a high surface area textured side (215) opposite the first copper layer. The bimetal foil further includes an aluminum oxide layer (305) on the high surface area textured side of the aluminum layer, a conductive polymerlayer (420) on the aluminum oxide layer, and a second copper layer (535) overlying the aluminum oxide layer. The bimetal foil may be embedded in a circuit board (700) to form high value embedded capacitors.

Abstract: A high impedance surface (300) has a printed circuit board (302) with a first surface (314) and a second surface (316), and a continuous electrically conductive plate (319) disposed on the second surface (316) of the printed circuit board (302). A plurality of electrically conductive plates (318) is disposed on the first surface (314) of the printed circuit board (302), while a plurality of elements are also provided. Each element comprises at least one of (1) at least one multi-layer inductor (330, 331) electrically coupled between at least two of the electrically conductive plates (318) and embedded within the printed circuit board (302), and (2) at least one capacitor (320) electrically coupled between at least two of the electrically conductive plates (318).

Abstract: A method is disclosed for fabricating a patterned embedded capacitance layer. The method includes fabricating (1305, 1310) a ceramic oxide layer (510) overlying a conductive metal layer (515) overlying a printed circuit substrate (505), perforating (1320) the ceramic oxide layer within a region (705), and removing (1325) the ceramic oxide layer and the conductive metal layer in the region by chemical etching of the conductive metal layer. The ceramic oxide layer may be less than 1 micron thick.

Abstract: A dielectric circuit board foil (400, 600) includes a conductive metal foil layer (210, 660), a crystallized dielectric oxide layer (405, 655) disposed adjacent a first surface of the conductive metal foil layer, a lanthanum nickelate layer (414, 664) disposed on the crystallized dielectric oxide layer, and an electrode layer (415, 665) that is substantially made of one or more base metals disposed on the lanthanum nickelate layer. The foil (400, 600) may be adhered to a printed circuit board sub-structure (700) and used to economically fabricate a plurality of embedded capacitors, including isolated capacitors of large capacitive density (>1000 pf/mm2).

Abstract: One of a plurality of capacitors embedded in a printed circuit structure includes a first electrode (415) overlaying a first substrate layer (505) of the printed circuit structure, a crystallized dielectric oxide core (405) overlaying the first electrode, a second electrode (615) overlying the crystallized dielectric oxide core, and a high temperature anti-oxidant layer (220) disposed between and contacting the crystallized dielectric oxide core and at least one of the first and second electrodes. The crystallized dielectric oxide core has a thickness that is less than 1 micron and has a capacitance density greater than 1000 pF/mm2. The material and thickness are the same for each of the plurality of capacitors. The crystallized dielectric oxide core may be isolated from crystallized dielectric oxide cores of all other capacitors of the plurality of capacitors.

Abstract: Thin film ceramic foil capacitors are mass-produced using inline reel-to-reel processing techniques by starting (100) with a length of copper foil which serves as one plate of the capacitor, then depositing (120) a layer of a ceramic precursor on a portion of one side of the copper foil at a first station. The foil is advanced (117, 127, 137, 147) to the next station where the ceramic precursor and the copper foil are heated (130) to remove any carrier solvents or vehicles, then pyrolyzed (140) to remove any residual organic materials. It is then sintered (150) at high temperatures to convert the ceramic to polycrystalline ceramic. A final top metal layer is then deposited (160) on the polycrystalline ceramic to form the other plate of the capacitor.

Abstract: High quality epitaxial layers of monocrystalline materials (26) can be grown overlying monocrystalline substrates (22) such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. An accommodating buffer layer (24) comprises a layer of monocrystalline oxide spaced apart from a silicon wafer by an amorphous interface layer (28) of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. Some preferred electronic devices are described that use a layer or pattern of a perovskite cuprate (2125, 2305, 2310, 2315, 2405) such as YBa2Cu3O7−y(YBCO) or Y1−xPrxBa2Cu3O7−y(YPBCO, 0<x<1) over a buffer layer (2120) of lanthanum strontium aluminum tantalate (LSAT).

Abstract: High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. An accommodating buffer layer comprises a layer of monocrystalline oxide spaced apart from a silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. In addition, formation of a compliant substrate may include utilizing surfactant enhanced epitaxy and epitaxial growth of single crystal silicon onto single crystal oxide materials. Monocrystalline substrates having a hydrogen ion implant are cleaved along the hydrogen ion implant, and an insulating substrate is bonded to the monocrystalline oxide.