Patents by Inventor Robert Currier

Robert Currier has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240266406
    Abstract: A transistor device includes a semiconductor substrate and a gate structure formed over the substrate. When fabricating the transistor device, at least one dielectric layer may be formed over ohmic contact structures of the transistor device, which may mitigate migration of material, such as metal, from the ohmic contact structures onto sensitive surfaces of the transistor device during subsequent fabrication processes. The transistor device may include one or more dielectric spacers, including at least one dielectric spacer disposed at a side wall of a gate channel through which gate structure contacts the substrate. The transistor device may include a field plate formed at least partially over the gate structure, the field plate having one or more stepped portions, which may improve linearity performance of the transistor device.
    Type: Application
    Filed: February 8, 2023
    Publication date: August 8, 2024
    Inventors: Congyong Zhu, Darrell Glenn Hill, David Robert Currier
  • Publication number: 20230129445
    Abstract: The system and method for providing antimicrobial and/or antiviral characteristics to substrates via an additive process for providing safe handling and reduction of cross contaminations from person to person from handling, shipping, storage and use of papers, boxes, liners, hospital barriers, respirator filters and liners, hospital curtains, masks, draperies, bed liners, and the like.
    Type: Application
    Filed: March 5, 2021
    Publication date: April 27, 2023
    Applicant: Performance Chemicals LLC
    Inventors: Michael CURRIER, Matthew CURRIER, Sarah A. Currier, Robert CURRIER
  • Patent number: 11450616
    Abstract: A method of making a semiconductor device is provided for depositing, patterning, and developing photoresist (1703, 1704) on an underlying layer located on a backside of a wafer having a frontside on which an integrated circuit die are formed over a shared wafer semiconductor substrate and arranged in a grid, thereby forming a patterned photoresist mask with a unique set of one or more openings which are used to selectively etch the underlying layer to form, on each integrated circuit die, a unique die mark identifier pattern of etched openings in the underlying layer corresponding to the unique set of one or more openings in the patterned photoresist mask (1705), where the patterned photoresist mask is removed (1706) from the backside of the wafer before singulating the wafer to form a plurality of integrated circuit devices (1708) which each include a unique die marking.
    Type: Grant
    Filed: July 29, 2020
    Date of Patent: September 20, 2022
    Assignee: NXP USA, INC.
    Inventors: David Robert Currier, Darrell Glenn Hill, Fred Reece Clayton, Alan J. Magnus, Warren Crapse
  • Publication number: 20220037264
    Abstract: A method of making a semiconductor device is provided for depositing, patterning, and developing photoresist (1703, 1704) on an underlying layer located on a backside of a wafer having a frontside on which an integrated circuit die are formed over a shared wafer semiconductor substrate and arranged in a grid, thereby forming a patterned photoresist mask with a unique set of one or more openings which are used to selectively etch the underlying layer to form, on each integrated circuit die, a unique die mark identifier pattern of etched openings in the underlying layer corresponding to the unique set of one or more openings in the patterned photoresist mask (1705), where the patterned photoresist mask is removed (1706) from the backside of the wafer before singulating the wafer to form a plurality of integrated circuit devices (1708) which each include a unique die marking.
    Type: Application
    Filed: July 29, 2020
    Publication date: February 3, 2022
    Applicant: NXP USA, Inc.
    Inventors: David Robert Currier, Darrell Glenn Hill, Fred Reece Clayton, Alan J. Magnus, Warren Crapse
  • Patent number: 9015662
    Abstract: Embodiments are directed to declaratively managing software applications, dynamically applying configuration changes to a specified software application based on a service level objective (SLO) and to efficiently performing an impact analysis for a specified service level agreement SLO.
    Type: Grant
    Filed: March 6, 2014
    Date of Patent: April 21, 2015
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: John M. Oslake, Subramanian Muralidhar, Richard Shawn Bice, Jeffrey Robert Currier, Narayan Mohanrao Nevrekar, Kenneth Van Hyning
  • Publication number: 20140189639
    Abstract: Embodiments are directed to declaratively managing software applications, dynamically applying configuration changes to a specified software application based on a service level objective (SLO) and to efficiently performing an impact analysis for a specified service level agreement SLO.
    Type: Application
    Filed: March 6, 2014
    Publication date: July 3, 2014
    Inventors: John M. Oslake, Subramanian Muralidhar, Richard Shawn Bice, Jeffrey Robert Currier, Narayan Mohanrao Nevrekar, Kenneth Van Hyning
  • Patent number: 8707254
    Abstract: Embodiments are directed to declaratively managing software applications, dynamically applying configuration changes to a specified software application based on a service level objective (SLO) and to efficiently performing an impact analysis for a specified service level agreement SLO.
    Type: Grant
    Filed: April 6, 2012
    Date of Patent: April 22, 2014
    Assignee: Microsoft Corporation
    Inventors: John M. Oslake, Subramanian Muralidhar, Richard Shawn Bice, Jeffrey Robert Currier, Narayan Mohanrao Nevrekar, Kenneth Van Hyning
  • Publication number: 20130268914
    Abstract: Embodiments are directed to declaratively managing software applications, dynamically applying configuration changes to a specified software application based on a service level objective (SLO) and to efficiently performing an impact analysis for a specified service level agreement SLO.
    Type: Application
    Filed: April 6, 2012
    Publication date: October 10, 2013
    Applicant: MICROSOFT CORPORATION
    Inventors: John M. Oslake, Subramanian Muralidhar, Richard Shawn Bice, Jeffrey Robert Currier, Narayan Mohanrao Nevrekar, Kenneth Van Hyning
  • Publication number: 20070220653
    Abstract: The disclosure is directed to an integrated glove including first and second substrate layers. The first substrate layer overlies the second substrate layer to define a volume therebetween configured to receive a wearer's hand. The integrated glove also includes first and second gas impermeable barrier layers respectively melt laminated to the first and second substrate layers. The first and second gas impermeable barrier layers extend beyond an outer contour of the first and second substrate layers and are melt laminated together to form a seam portion. The integrated glove has a breakthrough time greater than 60 minutes when exposed to NFPA 1991 industrial chemicals.
    Type: Application
    Filed: October 18, 2004
    Publication date: September 27, 2007
    Applicant: SAINT-GOBAIN PERFORMANCE PLASTICS CORPORATION
    Inventors: David Mack, Peter Kirk, Robert Currier