Abstract: A cache memory includes a plurality of memory chips, or other separately addressable memory sections, which are configured to collectively store a plurality of cache lines. Each cache line includes data and an associated cache tag. The cache tag may include an address tag which identifies the line as well as state information indicating the coherency state for the line. Each cache line is stored across the memory chips in a row formed by corresponding entries (i.e., entries accessed using the same index address). The plurality of cache lines is grouped into separate subsets based on index addresses, thereby forming several separate classes of cache lines. The cache tags associated with cache lines of different classes are stored in different memory chips. During operation, the cache controller may receive multiple snoop requests corresponding to, for example, transactions initiated by various processors.

Abstract: A system may include a plurality of nodes coupled by an inter-node network. Each of the nodes includes several active devices, an interface to the inter-node network, and an address network coupling the active devices to the interface. An active device included in one of the nodes initiates a transaction by sending either a first type of address packet or a second type of address packet on the address network dependent on whether the active device is included in a multi-node system. The first type of address packet is sent if the active device is included in a multi-node system and is not snooped by other active devices in the same node as the active device. The second type of address packet, sent if the active device is included in a single node system, is snooped by other active devices in the same node as the active device.

Abstract: A node for use in a multi-node computer system includes: a plurality of active devices; an interface configured to send and receive coherency messages on an inter-node network coupling nodes in the multi-node computer system; an address network configured to communicate address packets between the active devices and the interface; and a data network configured to communicate data packets between the active devices and the interface. The active device includes a promise array configured to store a promise identifying a data packet to be conveyed to a device in response to a pending local transaction involving a coherency unit for which the active device has an ownership responsibility. The active device is configured to store promises in the promise array in response to receiving address packets from other ones of the plurality of active devices and from the interface.

Abstract: A node includes several devices including a memory, an active device, and an interface configured to send and receive coherency messages on an inter-node network coupling the node to another node, as well as an address network that communicates address packets between the devices. In response to receiving a coherency message that requests an access right to a coherency unit, the interface sends a proxy packet on the address network. In response to the proxy packet, the memory sends the interface data corresponding to the coherency unit and an indication of the global access state of the coherency unit within the node if the global access state is not the modified state. Otherwise, the memory sends an additional proxy packet on the address network. If the active device is the owner of the coherency unit, the active device ignores the proxy packet and responds to the additional proxy packet.

Abstract: A system may include a node and an additional node coupled by an inter-node network. The node may include an active device, an interface to the inter-node network, a memory, and an address network coupling the active device, the interface, and the memory. The active device may send an address packet to initiate a transaction to gain an access right to a coherency unit. In response to receiving the address packet, the memory is configured to send data corresponding to the coherency unit to the active device dependent on memory response information associated with the coherency unit. If the transaction cannot be satisfied within the node, the memory is configured to forward a report corresponding to the address packet to the interface. In response to the report, the interface is configured to send the additional node a coherency message requesting the access right via the inter-node network.

Abstract: A system and method for improving the isolation and diagnosis of hardware faults in a computing system wherein means are provided for indicating whether unusable data has previously triggered diagnosis of the hardware fault that caused the data to be unusable. If diagnosis has not been performed, the flag is not set. If diagnosis has already been performed, the flag is set. One embodiment comprises an interface which is used to convey data from one subsystem to another. When the interface receives data from the first subsystem, the data is examined to determine whether it contains an uncorrectable error (including missing data.) If the data contains an uncorrectable error, the interface examines the flag corresponding to the data to determine whether hardware fault diagnosis has already been initiated. If diagnosis has already been initiated, the data is passed to the second subsystem without initiating further diagnosis.

Abstract: A cache memory includes a plurality of memory chips, or other separately addressable memory sections, which are configured to collectively store a plurality of cache lines. Each cache line includes data and an associated cache tag. The cache tag may include an address tag which identifies the line as well as state information indicating the coherency state for the line. Each cache line is stored across the memory chips in a row formed by corresponding entries (i.e., entries accessed using the same index address). The plurality of cache lines is grouped into separate subsets based on index addresses, thereby forming several separate classes of cache lines. The cache tags associated with cache lines of different classes are stored in different memory chips. During operation, the cache controller may receive multiple snoop requests corresponding to, for example, transactions initiated by various processors.

Abstract: A cache memory includes a plurality of memory chips, or other separately addressable memory sections, which are configured to collectively store a plurality of cache lines. Each cache line includes data and an associated cache tag. The cache tag may include an address tag which identifies the line as well as state information indicating the coherency state for the line. Each cache line is stored across the memory chips in a row formed by corresponding entries (i.e., entries accessed using the same index address). The plurality of cache lines is grouped into separate subsets based on index addresses, thereby forming several separate classes of cache lines. The cache tags associated with cache lines of different classes are stored in different memory chips. During operation, the cache controller may receive multiple snoop requests corresponding to, for example, transactions initiated by various processors.

Abstract: A system and method for improving the isolation and diagnosis of hardware faults in a computing system wherein means are provided for indicating whether unusable data has previously triggered diagnosis of the hardware fault that caused the data to be unusable. If diagnosis has not been performed, the flag is not set. If diagnosis has already been performed, the flag is set. One embodiment comprises an interface which is used to convey data from one subsystem to another. When the interface receives data from the first subsystem, the data is examined to determine whether it contains an uncorrectable error (including missing data.) If the data contains an uncorrectable error, the interface examines the flag corresponding to the data to determine whether hardware fault diagnosis has already been initiated. If diagnosis has already been initiated, the data is passed to the second subsystem without initiating further diagnosis.

Abstract: A data block includes a plurality of sub-blocks. Each sub-block includes a sub-block check bit that may be used to detect the presence of a bit error within the sub-block. A composite sub-block is generated, which is the column-wise exclusive-or of the bits of each sub-block. In one embodiment, the composite sub-block is not stored, but rather used for computational purposes only. A plurality of composite check bits is used to detect a bit position of a bit error within the composite sub-block. If a bit error within the data block occurs, the sub-block check bits may be used to detect in which sub-block the error occurred. The composite check bits may be used to determine which bit position of the composite sub-block is erroneous. The erroneous bit position of the composite sub-block also identifies the bit position of the erroneous bit in the sub-block identified by the sub-block check bits.

Abstract: A technique to detect and correct single bit errors and to detect paired bit errors in a data block. Two bits of the data block are paired and transferred on the same data path in different cycles. Check bits are computed prior to transferring the data block. A syndrome bits vector is computed when the data block is received. The syndrome bits vector includes a number of syndrome bits that is identical to the number of check bits. A value of the syndrome bits vector is used to detect and correct single bit errors and to detect paired double bit errors that occur in the data block without using an extended check bit. If the syndrome bits vector contains all zero bits, the data block is accepted without modification. If the syndrome bits vector is identical to a predetermined special vector V, a paired double bit error has occurred and either an unrecoverable error message is generated or a re-operation on the data block is requested.

Abstract: A system and method for improving the isolation and diagnosis of hardware faults in a computing system wherein means are provided for indicating whether unusable data has previously triggered diagnosis of the hardware fault that caused the data to be unusable. If diagnosis has not been performed, the flag is not set. If diagnosis has already been performed, the flag is set. One embodiment comprises an interface which is used to convey data from one subsystem to another. When the interface receives data from the first subsystem, the data is examined to determine whether it contains an uncorrectable error (including missing data.) If the data contains an uncorrectable error, the interface examines the flag corresponding to the data to determine whether hardware fault diagnosis has already been initiated. If diagnosis has already been initiated, the data is passed to the second subsystem without initiating further diagnosis.

Abstract: A multiprocessor computer system is configured to selectively transmit address transactions using either a broadcast mode or a point-to-point mode. Depending on the mode of transmission selected, either a directory-based coherency protocol or a broadcast snooping coherency protocol is implemented to maintain coherency within the system. A computing node is formed by a group of clients which share a common address and data network. The address network is configured to determine whether a particular transaction is to be conveyed in broadcast mode or point-to-point mode. In one embodiment, the address network includes a mode table with entries which are configurable to indicate transmission modes corresponding to different regions of the address space within the node. Upon receiving a coherence request transaction, the address network may then access the table in order to determine the transmission mode, broadcast or point-to-point, which corresponds to the received transaction.

Abstract: An apparatus and method for expediting the processing of requests in a multiprocessor shared memory system. In a multiprocessor shared memory system, requests can be processed in any order provided two rules are followed. First, no request that grants access rights to a processor can be processed before an older request that revokes access rights from the processor. Second, all requests that reference the same cache line are processed in the order in which they arrive. In this manner, requests can be processed out-of-order to allow cache-to-cache transfers to be accelerated. In particular, foreign requests that require a processor to provide data can be processed by that processor before older local requests that are awaiting data. In addition, newer local requests can be processed before older local requests. As a result, the apparatus and method described herein may advantageously increase performance in multiprocessor shared memory systems by reducing latencies associated with a cache consistency protocol.

Abstract: The bits of a data block are assigned to a plurality of logical groups such that at most one bit corresponding to a component is assigned to a logical group. This assignment ensures that a component failure may introduce at most one bit error to a logical group. A number of bits in a logical group is selected to reduce the number of check bits for a given number of data bits. Error correction may be performed within each logical group to correct single errors within the logical group. Because each logical group is assigned at most one bit corresponding to a component, component failures may be detected and corrected.

Abstract: A system for protecting data and correcting bit errors due to component failures includes a check bits generation unit which receives and encodes data to be protected. The check bits generation unit effectively partitions the data into a plurality of logical groups. The check bits generation unit generates a parity bit for each of the logical groups, and additionally generates a global error correction. The global error correction code is equivalent to the result of generating individual error correction codes for each logical group and combining them in a predetermined manner. An error correction unit is coupled to receive the plurality of data bits and the check bits following storage or transmission. A global syndrome code is generated such that, with knowledge of the specific logical groups that have a single bit error, a value indicative of the location of the error in such groups may be derived from the global syndrome code.

Abstract: A system for detecting and correcting errors in a data block includes a check bits generation unit which receives and encodes data to be protected. The check bits generation unit effectively partitions the data into a plurality of logical groups. The check bits generation unit generates a parity bit for each of the logical groups, and additionally generates a pair of global error correction codes, referred to generally as an untwisted global error correction code and a twisted global error correction code. Data at corresponding bit positions within the logical groups are conveyed through a common component. The untwisted global error correction code may be equivalent to the result of generating an individual error correction code for each logical group and XORing the collection of individual error correction codes together.

Abstract: A mechanism for decoding linear shifted codes employs two shift registers. The shift registers are independently controlled by an associated control unit. Initially, the received parity bits are stored in a first shift register and the global syndrome bits are stored in a second shift register. While the right-most cell in the first shift register contains a logical “0”, both shift registers are shifted right one position. When the right-most cell of the first shift register contains a “1”, the content of the right-most cell of the second shift register is recorded as a first bit of a syndrome code which identifies the position of an error with any groups with an error. If the value recorded is a “1”, a bit-wise exclusive OR operation is then performed on the values in the first and second shift registers, and the result is stored in the second shift register. Subsequently, the contents of the second shift register are shifted by one position.

Abstract: A data block includes a plurality of sub-blocks. Each sub-block includes a sub-block check bit that may be used to detect the presence of a bit error within the sub-block. A composite sub-block is generated, which is the column-wise exclusive-or of the bits of each sub-block. In one embodiment, the composite sub-block is not stored, but rather used for computational purposes only. A plurality of composite check bits is used to detect a bit position of a bit error within the composite sub-block. If a bit error within the data block occurs, the sub-block check bits may be used to detect in which sub-block the error occurred. The composite check bits may be used to determine which bit position of the composite sub-block is erroneous. The erroneous bit position of the composite sub-block also identifies the bit position of the erroneous bit in the sub-block identified by the sub-block check bits.

Abstract: The bits of a data block are assigned to a plurality of logical groups such that at most one bit corresponding to a component is assigned to a logical group. This assignment ensures that a component failure may introduce at most one bit error to a logical group. A number of bits in a logical group is selected to reduce the number of check bits for a given number of data bits. Error correction may be performed within each logical group to correct single errors within the logical group. Because each logical group is assigned at most one bit corresponding to a component, component failures may be detected and corrected.