Abstract: A method for forming a structure having lightning strike protection includes receiving at least one structural layer, receiving at least one lightning strike protection strip disposed on at least one reinforcement layer, automatically applying the at least one lightning strike protection strip disposed on the at least one reinforcement layer onto the at least one structural layer, and forming the at least one structural layer, the at least one lightning strike protection strip, and the at least one reinforcement layer, into the structure. The at least one lightning strike protection strip comprises a first material, and the at least one reinforcement layer comprises a second material different from the first material. The automatically applying may include using at least one of fiber placement equipment, tape laying equipment, and similar automated equipment.

Abstract: A method for forming a structure having lightning strike protection includes receiving at least one structural layer, receiving at least one lightning strike protection strip disposed on at least one reinforcement layer, automatically applying the at least one lightning strike protection strip disposed on the at least one reinforcement layer onto the at least one structural layer, and forming the at least one structural layer, the at least one lightning strike protection strip, and the at least one reinforcement layer, into the structure. The at least one lightning strike protection strip comprises a first material, and the at least one reinforcement layer comprises a second material different from the first material. The automatically applying may include using at least one of fiber placement equipment, tape laying equipment, and similar automated equipment.

Abstract: A calculator mount includes a self closing hinge with a frame wing and a door wing. The frame wing is attached to a desk with a top and overhang, and a calculator mounting bracket is carried by the door wing. The door wing and bracket swing between a position at which the calculator is at a position adjacent the top surface of the desk and a position at which it folds under the desk. It can be mounted on either side of the desk.

Abstract: A memory control unit (MCU) 22 includes a first interface for interfacing the memory control unit to one or more memory units; a second interface for interfacing the memory control unit to a system bus, including a system data bus for expressing information units, including memory read and write requests, and a system address bus. The MCU further includes logic, responsive to a write request from the system bus, for storing one or more information units within a memory unit at an address specified by the system address bus. The storing logic includes write request receiving and buffer logic having a plurality of storage locations for storing received write requests and associated write addresses prior to the execution of the write requests. The MCU further includes logic, responsive to a read request from the system bus, for reading one or more information units from a memory unit at a location specified by the system address bus.

Abstract: A system bus 12 for an information processing system 10 includes a first group of signal lines 16 whereon command/ID information is time multiplexed with data, and a second group of signal lines 14 for conveying address information. During a first bus cycle command/ID information is presented on the first group of signal lines while the address is presented on the second group of signal lines. During a subsequent bus cycle, and for a data write or data return operation, the first group of signal lines conveys data. Other bus connections, such as cache memories, are thus apprised of the address a full bus cycle before the data is presented thereby providing the bus connections with sufficient time to decode and otherwise operate on the bus information. Multiple word data returns from a system memory are characterized as having the address associated with a particular word of data presented in the immediately prior bus cycle, facilitating the pipelining of data and address information through the system bus.

Abstract: A method and apparatus for saving memory space in a buffer whereby the valid bit in the entry of the translation lookaside buffer for a cache memory is collapsed into one of the level bits indicating the length of the virtual address. During the lookup of the translation lookaside buffer, the virtual address in each entry is compared with the virtual address from the CPU if the level/valid bit is set, i.e. the entry is valid. If the level/valid bit is not set, then no compare takes place and the lookup continues to the next entry. The length of the virtual address to be compared is further determined by the status of the remaining level bits.

Abstract: A system having a CPU, a main memory and a bus. A cache memory couples the CPU to the bus and is provided with circuitry to indicate the status of a data unit stored within the cache memory. One status indication indicates whether the contents of a storage position have been modified (dirty) since those contents were received from main memory. Another status indication indicates whether the contents of the storage position exist within another cache memory (shared). Each cache includes a bus monitor that monitors bus transactions. When data is read from system memory by a first cache a second cache determines if the data is shared. If yes, the second cache asserts a bus hold line and determines if the shared data is dirty. If yes, the second cache drives the corresponding data to the bus for storage within the first cache. For a system memory write, the second cache latches the data and determines if the data is shared. If yes, the second cache replaces its copy of the data with that latched from the bus.

Abstract: Apparatus for executing a conditional branch instruction in a pipelined processing unit which has an instruction queue for storing an instruction stream, address generating apparatus connected to the head of the instruction queue for generating and retaining an address defined in the portion of the instruction stream presently at the head of the instruction queue, and instruction interpretation apparatus which is also connected to the head of the instruction queue for receiving and interpreting an instruction at the head of the instruction queue. A conditional branch instruction which is presently at the head of the instruction queue is executed by first performing a dispatch operation in a first cycle which is the last cycle of execution of the instruction preceding the conditional branch instruction in the instruction queue. The dispatch operation sets up the execution of the instruction at the head of the instruction queue.

Abstract: A system console 30 is enabled to read registers from memory boards 12 and 14 and to set registers within the memory boards which control the disabling of one or more memory arrays 16-22. The information read from the memory boards is indicative at least of which of the memory arrays has malfunctioned. The registers are within a memory logic array 40, one of which is disposed upon each of the memory boards 12 and 14 and also upon a memory controlling unit 26, the memory logic arrays being coupled together by a bit serial scan bus 42. In a preferred embodiment of the invention the memory logic arrays 40 are comprised of a highly integrated gate array semiconductor device, each of which is identical. Each memory logic array is provided with a base address input from a preceding memory logic array and computes a base address for a subsequent memory logic array.

Abstract: A system is described wherein a CPU, a main memory means and a bus means are provided. Cache memory means is employed to couple the CPU to the bus means and is further provided with means to indicate the status of a data unit stored within the cache memory means. One status indication tells whether the contents of a storage position have been modified since those contents were received from main memory and another indicates whether the contents of the storage position may be present elsewhere memory means. Control means are provided to assure that when a data unit from a CPU is received and stored in the CPU's associated cache memory means, which data unit is indicated as being also stored in a cache memory means associated with another CPU, such CPU data unit is also written into main memory means. During that process, other cache memory means monitor the bus means and update its corresponding data unit.

Abstract: A spray gun quickly convertible between an airless non-fogging mode and a fogging or air mode when using a fog dispensing wand accessory. The hand grip is formed in part by a valve housing for the liquid component and, in part, by the overlapping ends of a pair of valve control levers for the gun. The fog generating chamber embraces the spray nozzle of the spray gun, and is formed within the coupling holding the fog dispensing wand detachably assembled over the spray nozzle.