Patents by Inventor Robert D. Berger

Robert D. Berger has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5627492
    Abstract: An integrated circuit is divided into functional blocks. The integrated circuit includes current source based circuitry such as Emitter Coupled Logic (ECL), Current Mode Logic (CML), or Source Coupled Logic (SCL) Isolation blocks (14-20) are placed in signal paths to and from each functional block. A multiple output bias driver circuit (13) couples to each functional block. The multiple output bias driver circuit (13) provides a signal for enabling and disabling current sources of a functional block. A bias control logic circuit (12) controls the isolation blocks (14-20) and the multiple output bias driver (13). A functional block that is idle in the operation of the integrated circuit is shut down by the bias control logic circuit (12) to conserve power. The multiple output bias driver circuit (13) receives control signals from the bias control logic circuit (12) to turn off current sources in the idle functional block.
    Type: Grant
    Filed: November 3, 1995
    Date of Patent: May 6, 1997
    Assignee: Motorola, Inc.
    Inventors: Mark Weaver, Robert D. Berger, Dwight D. Esgar
  • Patent number: 5001370
    Abstract: A high speed voltage translator is responsive to an ECL input signal for providing a TTL output signal at an output while clamping the low output voltage thereof to a predetermined value. The ECL input signal is converted to first and second complementary control signals for driving the upper and lower transistors in the output stage, respectively. The second control signal enables a third transistor, the base of which is connected via a serial diode and resistor combination to a second collector of the lower transistor in the output stage. The base-emitter junction potential of the third transistor cancels the potential across the diode whereby the collector of the lower transistor that is the output of the voltage translator is clamped at one base-emitter junction potential less the voltage across the resistor. Furthermore, the current flowing through the resistor is compensated for temperature variation whereby the low output voltage is independent of temperature.
    Type: Grant
    Filed: July 2, 1990
    Date of Patent: March 19, 1991
    Assignee: Xerox Corporation
    Inventors: M. Nghiem Phan, Robert D. Berger