Abstract: A multiple function image capture and serving apparatus that comprises a processor unit having firmware memory with instructions for implementing an operating system and random access memory for receiving at least one executable code sections for performing a selected one of a plurality of image capture tasks; a network access module for communicatively connecting the processor unit to an ICA code server, wherein the processor unit in response to executing the operating system and selection of the task by a user is adapted to request and receive from the server at least one executable code sections for performing the selected task; and an image capture module for receiving and converting a visual image into a digital image signal and making said signal available to the processor unit for performing upon it the selected task pursuant to execution of the at least one received executable code sections.

Abstract: Generally, graphics are displayed on a monitor or printed on an output device after a series of steps are performed, typically implemented in the form of a graphics pipeline, in the case of an object-oriented graphic image. Similarly, a digital picture or digital video image passes through a digital pipeline for the digital image or images to be displayed, printed, or otherwise processed. The present invention encompasses a system and method in which the stages of the graphics pipeline used to process a graphic object are interconnected to the stages of the digital pipeline used to process a bit-mapped image so that a single, interconnected pipeline can be used to process object-oriented graphic images, bit map images and/or images which contain graphics and bit map portions. This interconnected pipeline can be used to process images through various stages of the graphics pipeline followed by stages typically contained in the digital pipeline, or vice versa, to create desired effects.

Abstract: A system and method of evaluating cache coherency protocols and algorithms in scalable symmetric multiple processor computer systems. The system includes scalable 32-byte or larger cache lines wherein one specific byte in the cache line is assigned for write and read transactions for each specific 32-bit processor. The method includes steps to ensure each 32-bit processor writes and reads to and from the specific byte in the cache line assigned to that 32-bit processor.

Abstract: A system and method of evaluating cache coherency protocols and algorithms in scalable symmetric multiple processor computer systems. The system includes scalable 32-byte or larger cache lines wherein one specific byte in the cache line is assigned for write and read transactions for each specific 32-bit processor. The method includes steps to ensure each 32-bit processor writes and reads to and from the specific byte in the cache line assigned to that 32-bit processor.

Abstract: A multiple function image capture and serving apparatus that comprises a processor unit having firmware memory with instructions for implementing an operating system and random access memory for receiving at least one executable code sections for performing a selected one of a plurality of image capture tasks; a network access module for communicatively connecting the processor unit to an ICA code server, wherein the processor unit in response to executing the operating system and selection of the task by a user is adapted to request and receive from the server at least one executable code sections for performing the selected task; and an image capture module for receiving and converting a visual image into a digital image signal and making said signal available to the processor unit for performing upon it the selected task pursuant to execution of the at least one received executable code sections.

Abstract: A system and method of evaluating cache coherency protocols and algorithms in scalable symmetric multiple processor computer systems. The system includes scalable 32-byte or larger cache lines wherein one specific byte in the cache line is assigned for write and read transactions for each specific 32-bit processor. The method includes steps to ensure each 32-bit processor writes and reads to and from the specific byte in the cache line assigned to that 32-bit processor.

Abstract: The present invention encompasses a system and method in which networked appliances communicate with each other over a local area network as equals without the requirement of a supervising personal computer. The invention incorporates communication capabilities within each of the networked appliances and unique identifiers and enables the appliances themselves to communicate and exchange data, and access a wide area network such as the Internet. The networked appliances communicate with each others as peers rather than through a personal computer or central server. A network appliance of the present invention includes a memory, a data interface to a local area network and a controller.

Abstract: A system and method of evaluating cache coherency protocols and algorithms in scalable symmetric multiple processor computer systems. The system includes scalable 32-byte or larger cache lines wherein one specific byte in the cache line is assigned for write and read transactions for each specific 32-bit processor. The method includes steps to ensure each 32-bit processor writes and reads to and from the specific byte in the cache line assigned to that 32-bit processor.

Abstract: Generally, graphics are displayed on a monitor or printed on an output device after a series of steps are performed, typically implemented in the form of a graphics pipeline, in the case of an object-oriented graphic image. Similarly, a digital picture or digital video image passes through a digital pipeline for the digital image or images to be displayed, printed, or otherwise processed. The present invention encompasses a system and method in which the stages of the graphics pipeline used to process a graphic object are interconnected to the stages of the digital pipeline used to process a bit-mapped image so that a single, interconnected pipeline can be used to process object-oriented graphic images, bit map images and/or images which contain graphics and bit map portions. This interconnected pipeline can be used to process images through various stages of the graphics pipeline followed by stages typically contained in the digital pipeline, or vice versa, to create desired effects.

Abstract: A system and method for providing application software for a peripheral device to be installed in a computer system. The application software is rendered into a memory module coupled to the peripheral device. When the peripheral device is attached to the computer, the operating system of the computer queries the peripheral device. Responsive to the query, the peripheral device is operable to upload the application software into the computer system from the memory module.

Abstract: The present disclosure relates to an appliance configured for connection to a network and communication with a device connected to the network. In one embodiment, the appliance comprises a processing device configured to control operation of the appliance, memory including logic configured to receive software that facilitates communication between the appliance and the device from a software source, and network interface devices with which the appliance communicates with the software source.

Abstract: A photographic film unit comprising superposed photosensitive and image-viewing elements including an area adapted to be exposed and processed by an aqueous alkaline processing composition spread in a layer between the two elements to facilitate formation of a transfer image. A trap for excess processing compositon is affixed to one end of the unit and the entire assemblage is secured together by a binding element which is secured around and to at least three edges of the film unit including the edge to which is affixed the trap. The binding element comprises foldable tabs on both sides of the trap area and, when the element is folded to provide binding functionality, the tabs are located slightly inboard of the trap whereby the thickness of the film unit in the area of a tab is increased by the thickness of the tab.