Abstract: An algorithmic matching pipelined compiler and a reusable algorithmic pipelined core comprise a high throughput processor system. The reusable algorithmic pipelined core is a reconfigurable processing core with a pipelined structure comprising a processor with a setup interface for programming any of a plurality of operations as determined by setup data, a logic decision processor for programming a look up table, a loop counter and a constant register, and a block of memory. This can be used to perform functions. A reconfigurable, programmable circuit routes data and results from one core to another core and/or IO controller and/or interrupt generator, as required to complete an algorithm without further intervention from a central or peripheral processor during processing of an algorithm.

Abstract: An algorithmic matching pipelined compiler and a reusable algorithmic pipelined core comprise a high throughput processor system. The reusable algorithmic pipelined core is a reconfigurable processing core with a pipelined structure comprising a processor with a setup interface for programming any of a plurality of operations as determined by setup data, a logic decision processor for programming a look up table, a loop counter and a constant register, and a block of memory. This can be used to perform functions. A reconfigurable, programmable circuit routes data and results from one core to another core and/or IO controller and/or interrupt generator, as required to complete an algorithm without further intervention from a central or peripheral processor during processing of an algorithm.

Abstract: A disk drive is disclosed comprising a head actuated over a disk having a plurality of data tracks and a first and second set of reserved tracks, wherein the first set of reserved tracks are located at a first radial location, and the second set of reserved tracks are located at a second radial location different than the first radial location. A write command is received from a host, wherein the write command comprises user data which is stored in a cache memory. When a power failure is detected, whether the head is nearer to the first or second set of reserved tracks is determined, and then the head is positioned to the nearest of the first and second set of reserved tracks. The user data stored in the cache memory is written to the reserved tracks, and the head is unloaded onto a ramp.

Abstract: A method for verifying the design of a disk controller circuit to be incorporated into a targeted hard disk drive system having a read/write channel and a head actuator may include steps of emulating reading and writing of data in the read/write channel based upon a model of the read/write channel, emulating a behavior of the head actuator during track seek and track following operations based upon an electromechanical model of the head actuator, providing a disk controller design base for defining integrated circuit elements comprising the disk controller circuit and providing a controller environment to support execution and debug of firmware for operating the disk controller circuit. A plurality of disk functions may be carried out at a time-scaled rate according to a script. The plurality of disk functions includes interaction of at least the read/write model, the electromechanical model, the disk controller design base and the controller environment.

Abstract: Power measuring apparatus including a first multiplexor having its inputs responsive to the polyphase voltage and current inputs being measured. The multiplexor reads these inputs in sequence based on address signals provided by a program controlled microprocessor. The output of the multiplexor is coupled to an RMS to DC converter, the output of which is coupled to a second multiplexor. The voltage inputs are coupled to a voltage averaging device, the output thereof being coupled to additional inputs of the second multiplexor, the output of the second multiplexor being coupled to the microprocessor via an analog to digital converter. The microprocessor reads and compares the voltage output from the averaging circuit and the corresponding voltage at the output of the converter and generates a correction factor and responds thereto.

Abstract: A line adapter system for handling byte-oriented data transfers between remote data terminals and I/O subsystem. Working in conjunction with a controlling microprocessor, the line adapter provides input output means for regulating the baud rate of transmission to/from a remote terminal and for the timing and protocols required for both synchronous and asynchronous data transmission. The microprocessor may address and control various of the timing elements and byte to bit transfer means of the input/output circuit means. Likewise, each of the elements of the input/output circuit means may request service from the microprocessor for further detailed instructions.

Abstract: A testing circuit is disclosed for addressing and exercising a ROM-type memory and splitting the same memory output data into two paths. One path is used to temporarily hold the memory output data for a time-interval after which it is compared, in a digital comparator, with the same memory output data on the second path. When the data on both paths compare equally, then it is known that no instability has occurred during the time-interval. If a miscompare occurs, the comparator generates an error signal.

Abstract: An I/O subsystem uses a peripheral-controller for handling data transfer operations between a host computer and a plurality of peripheral terminals. The peripheral controller is made of (a) a universal processor, which generates instructions for executing data transfer operations, and (b) an application dependent logic module which particularly adapts the instructions to each peripheral terminal connected to the system. Upon recognition of the use of addresses for slow memories, slow registers or "slow devices", control logic in the application dependent logic module controls the clocking in the universal processor to slow data transfer rates for data being placed in or removed from the "slow devices".

Abstract: An interrupt network whereby, upon completion of a data transfer cycle between a host computer and peripheral-controller or completion of a data transfer cycle between a peripheral terminal and peripheral-controller, the peripheral-controller is placed in an interrupt mode (background mode) and institutes an interrupt service routine. The normal mode data in the peripheral-controller is stored for re-use upon return to normal mode.

Abstract: A line adapter unit working in conjunction with a microprocessor which serves to handle data transmission using the bit oriented protocol mode. The microprocessor can select any one of a plurality of input-output circuit units which provide specific control of communications to/from remote data terminals or data sets. The microprocessor can select and control various components of the input-output circuit means such as regulating the timing means and setting up command structures for controlling the type, the direction, and the conversion of serial bit data. Likewise, each component of an input-output circuit unit may request service via an interrupt to the microprocessor and receive a command or response required for further operations. Each input-output circuit unit is provided with a dedicated memory area associated with a given data communications line.

Abstract: Apparatus and a technique is disclosed for testing the access time of electronic storage arrays such as bistable storage cells fabricated in accordance with integrated circuit technology. A test pattern generator generates addresses on an "increment-complement" system and applies these addresses to a memory such as a PROM being tested. All combinations of the rows and columns of the PROM are exercised. Output data from the PROM is split into two separate buses which constitute a direct output bus and a delayed output bus. A first digital comparator compares the respective data signals for each output line on each of the buses in order to ensure that the "stabilized" output data corresponds exactly to the direct output data. A second digital comparator can be set to establish a standard for the minimum time period at which the output data from the tested PROM has become acceptably stabilized. Specialized clocking and controlled delay times are provided by a digital access control unit.

Abstract: A dual-processor, general purpose mini-computer which is programmed as a front-end data communications processor and is called a Network Support Processor. Data transfer commands received from a main host computer are executed and result messages are returned to the main host computer by the Network Support Processor. A base connection module providing slide-in connector cards houses and supports circuit cards which make up the Network Support Processor. These cards include a master controller which includes a master processor card, a master memory control card and an Interface Card which connects to a main host computer and to one or more line communications processors, each of which may handle up to 16 data communications lines. A slave controller likewise includes a slave processor circuit card, and a slave memory control circuit card. A series of slide-in memory cards forming a shared memory storage means connect to both the master and the slave memory control circuit cards.

Abstract: A test pattern generator is used for generating a series of address signals such as for exercising an integrated circuit memory. Master reference clock means are used to trigger a three stage counting circuit and also a circuit array of exclusive OR gates. The outputs of the stages of the counter provide individual inputs to each of the exclusive OR gates. The array of exclusive OR gates is arranged so that each exclusive OR gate has an output line which provides one bit of information for the address signals. The combination of the outputs of the OR gates forms a parallel bus which carries the address signals to be applied to the integrated circuit memory. The circuit generates a specialized address pattern in which the original address generated is complemented, then incremented on a series of increment-complement actions so that all combinations of the row and column drivers in the integrated circuit memory are exercised.

Abstract: Base connection modules are used to house slide-in cards which form a Network Support Processor which executes data transfer operations for up to four main host computers. One Network Support Processor can control up to four Line Support Processors, each one of which manages up to 16 Line Adapters connected, via data communication lines, to remote terminals. The line Support Processor, via its Line Adapters, handles a wide variety of communication line disciplines but provides a common discipline to its Network Support Processor and the host computer.

Abstract: A microprocessor system in which a microprocessor with a linear sequencing circuit works with arithmetic logic, program memory, registers, and other support circuitry to provide control lines and bus connections to an external application dependent logic module which has control logic, external registers and external memory and is oriented to handle the specific requirements for data transfers to and from a particular type of peripheral device. Means are provided in said microprocessor for selecting the number of times an instruction word is to be repeated and for the halting of a repeated instruction by internal or external means.

Abstract: A control circuit for generating first and second clocking pulses as outputs wherein there is a controlled time delay between the first and the second clocking pulses. The delay time, d.sub.i, between the first and second clocking pulses can be controlled as to the duration of the delay and also can be placed on an automatic sequence basis wherein the time delay d.sub.i period will automatically readjust to a series of smaller time delay periods.

Abstract: A microprocessor system works in conjunction with an application dependent logic module tailored to serve the particular requirements of a given peripheral device. The microprocessor is provided with a linear microsequencer circuit to operate with all types of application dependent logic modules and to provide instructions and control for data transfer operations. Means are provided in the microprocessor for operation in a "normal" mode whereby a first set of accumulator registers and flag registers are used exclusively, and in a "background" or interrupt mode where a second set of accumulator registers and flag registers are used exclusively.

Abstract: A microprocessor system having linear program sequencing and working in conjunction with an application dependent logic module tailored to handle the requirements of a variety of types of peripheral devices and wherein a microprocessor operates as a universal standard for all types of different application dependent logic modules. Means are provided for the microprocessor to access a total word from memory or to access any selected byte of a word in memory. Thus, the microprocessor and the application dependent logic module constitute a peripheral-controller which can control and monitor data transfer operations between a main host computer and a variety of peripheral devices whether such peripheral devices are "byte" oriented, such as card readers, or whether the peripheral terminal unit is "word" oriented such as magnetic tape or disk peripheral units.

Abstract: A microprocessor system comprising an arithmetical logic unit, a program memory and an external memory, memory address means (including a program counter and a memory reference register) for addressing either the program memory or the external memory. The microprocessor is sequenced by a linear sequencing circuit which can use different size plug-compatible PROMs. An instruction register receives instructions from either program memory or external memory along an instruction bus, which instructions are conveyed via a memory operand register to the arithmetic logic unit. The program memory is provided with a specialized instruction word format. The instruction word format provides: a single bit field for selecting either the program counter or the memory reference register as the source of memory addresses; it provides a function field which defines the route of data transfers to be made; and provides a "source and destination" field for addressing selected source and destination locations.

Abstract: A microprocessor system working in conjunction with an application dependent logic module tailored to handle the requirements of a variety of types of peripheral devices and wherein a microprocessor operates as a universal standard for all types of different application dependent logic modules. Means are provided for the microprocessor to access a total word from memory or to access any selected byte of a word in memory. Thus, the microprocessor and the application dependent logic module constitute a peripheral-controller which can control and monitor data transfer operations between a main host computer and a variety of peripheral devices whether such peripheral devices are "byte" oriented, such as card readers, or whether the peripheral terminal unit is "word" oriented such as magnetic tape or disk peripheral units.