Patents by Inventor Robert D. Colclasure

Robert D. Colclasure has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor device and alignment method
    Patent number: 6509247
    Abstract: A semiconductor wafer (101) includes a first semiconductor die (103) having a first alignment mark (165) disposed in an alignment region (163) to align the first semiconductor die on the wafer. A second semiconductor die (181) has a second alignment mark (167) disposed in the alignment region such that the second alignment mark overlaps the first alignment mark. The area occupied by the overlapping alignment marks is shared between the first and second semiconductor dice to reduce the area and the cost of each die.
    Type: Grant
    Filed: January 25, 2001
    Date of Patent: January 21, 2003
    Assignee: Motorola, Inc.
    Inventors: Gong Chen, Robert D. Colclasure
  • Semiconductor device and alignment method
    Publication number: 20010008790
    Abstract: A semiconductor wafer (101) includes a first semiconductor die (103) having a first alignment mark (165) disposed in an alignment region (163) to align the first semiconductor die on the wafer. A second semiconductor die (181) has a second alignment mark (167) disposed in the alignment region such that the second alignment mark overlaps the first alignment mark. The area occupied by the overlapping alignment marks is shared between the first and second semiconductor dice to reduce the area and the cost of each die.
    Type: Application
    Filed: January 25, 2001
    Publication date: July 19, 2001
    Inventors: Gong Chen, Robert D. Colclasure
  • Alignment method for semiconductor device
    Patent number: 6228743
    Abstract: A semiconductor wafer (101) includes a first semiconductor die (103) having a first alignment mark (165) disposed in an alignment region (163) to align the first semiconductor die on the wafer. A second semiconductor die (181) has a second alignment mark (167) disposed in the alignment region such that the second alignment mark overlaps the first alignment mark. The area occupied by the overlapping alignment marks is shared between the first and second semiconductor dice to reduce the area and the cost of each die.
    Type: Grant
    Filed: May 4, 1998
    Date of Patent: May 8, 2001
    Assignee: Motorola, Inc.
    Inventors: Gong Chen, Robert D. Colclasure