Patents by Inventor Robert D. Colclasure

Robert D. Colclasure has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6509247
    Abstract: A semiconductor wafer (101) includes a first semiconductor die (103) having a first alignment mark (165) disposed in an alignment region (163) to align the first semiconductor die on the wafer. A second semiconductor die (181) has a second alignment mark (167) disposed in the alignment region such that the second alignment mark overlaps the first alignment mark. The area occupied by the overlapping alignment marks is shared between the first and second semiconductor dice to reduce the area and the cost of each die.
    Type: Grant
    Filed: January 25, 2001
    Date of Patent: January 21, 2003
    Assignee: Motorola, Inc.
    Inventors: Gong Chen, Robert D. Colclasure
  • Publication number: 20010008790
    Abstract: A semiconductor wafer (101) includes a first semiconductor die (103) having a first alignment mark (165) disposed in an alignment region (163) to align the first semiconductor die on the wafer. A second semiconductor die (181) has a second alignment mark (167) disposed in the alignment region such that the second alignment mark overlaps the first alignment mark. The area occupied by the overlapping alignment marks is shared between the first and second semiconductor dice to reduce the area and the cost of each die.
    Type: Application
    Filed: January 25, 2001
    Publication date: July 19, 2001
    Inventors: Gong Chen, Robert D. Colclasure
  • Patent number: 6228743
    Abstract: A semiconductor wafer (101) includes a first semiconductor die (103) having a first alignment mark (165) disposed in an alignment region (163) to align the first semiconductor die on the wafer. A second semiconductor die (181) has a second alignment mark (167) disposed in the alignment region such that the second alignment mark overlaps the first alignment mark. The area occupied by the overlapping alignment marks is shared between the first and second semiconductor dice to reduce the area and the cost of each die.
    Type: Grant
    Filed: May 4, 1998
    Date of Patent: May 8, 2001
    Assignee: Motorola, Inc.
    Inventors: Gong Chen, Robert D. Colclasure
  • Patent number: 6218200
    Abstract: A multi-level registration control system for a photolithography process includes a photolithography device that prints first, second and third layers on a wafer. A first overlay mark defines overlay errors in a first direction between the first and third layer. The first overlay mark also defines overlay errors between the second and third layers. An overlay measurement device measures the overlay errors and generates an overlay signal. A feedback controller is connected to the overlay measurement device and the photolithography device. The feedback controller receives the overlay error signal and generates and transmits an alignment correction signal to the photolithography device. The first overlay mark is a box-in-box overlay mark or a frame-in-frame overlay mark. By providing a single overlay mark to align three layers, the multi-layer overlay control system reduces scribe grid area and saves useful silicone surface area.
    Type: Grant
    Filed: July 14, 2000
    Date of Patent: April 17, 2001
    Assignee: Motorola, Inc.
    Inventors: Gong Chen, Robert D. Colclasure, Jr., Wayne M. Paulson