Patents by Inventor Robert D. Fisch

Robert D. Fisch has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6981261
    Abstract: A method of performing a thread switching operation within a multithreaded processor. The dispatch of a first predetermined quantity of instruction information for a first thread, from an instruction streaming buffer to an instruction pre-decoder within the multithreaded processor, is detected. Responsive to the detection of the dispatch of the first predetermined quantity of instruction information for the first thread, a thread switching operation is performed with respect to the output of the instruction streaming buffer. The dispatch of instruction information for a second thread from the instruction streaming buffer is thus commenced. The utilization of processor resources is distributed between threads according to the quantity of instruction data for a particular thread that has been processed (or dispatch for processing), and not according to an arbitrary timing mechanism.
    Type: Grant
    Filed: September 20, 2002
    Date of Patent: December 27, 2005
    Assignee: Intel Corporation
    Inventors: Stavros Kalafatis, Alan B. Kyker, Robert D. Fisch
  • Patent number: 6971104
    Abstract: A method of performing a thread switching operation within a multithreaded processor includes detecting dispatch of a first predetermined quantity of instruction information of a first thread, from an instruction streaming buffer to an instruction pre-decoder within the multithreaded processor. Responsive to the detection of the dispatch of the first predetermined quantity of instruction information for the first thread, a thread switching operation is performed with respect to the output of the instruction streaming buffer. The dispatch of instruction information for a second thread from the instruction streaming buffer is thus commenced. The predetermined quantity of the instruction information may be equal to or greater than a minimum quantity of instruction information for a full instruction of a first instruction set.
    Type: Grant
    Filed: September 20, 2002
    Date of Patent: November 29, 2005
    Assignee: Intel Corporation
    Inventors: Stavros Kalafatis, Alan B. Kyker, Robert D. Fisch
  • Patent number: 6865740
    Abstract: A method of performing a thread switching operation within a multithreaded processor includes detecting the dispatch of a first predetermined quantity of instruction information of a first thread, from an instruction streaming buffer to an instruction pre-decoder within the multithreaded processor. Responsive to the detection of the dispatch of the first predetermined quantity of instruction information of the first thread, a thread switching operation is performed with respect to the output of the instruction streaming buffer. A flow marker is inserted into an instruction stream, the instruction stream including the instruction information of the first thread dispatched from the instruction information source, and the flow marker indicating that the thread switching operation has occurred. The dispatch of instruction information for a second thread from the instruction streaming buffer is thus commenced.
    Type: Grant
    Filed: September 20, 2002
    Date of Patent: March 8, 2005
    Assignee: Intel Corporation
    Inventors: Stavros Kalafatis, Alan B. Kyker, Robert D. Fisch
  • Patent number: 6854118
    Abstract: A method of performing a thread switching operation within a multithreaded processor includes detecting dispatch of a first predetermined quantity of instruction information of a first thread, from an instruction streaming buffer to an instruction pre-decoder within the multithreaded processor. A flow marker within instruction information for the first thread received at the instruction information source is also detected. Responsive to the detection of the dispatch of the first predetermined quantity of instruction information of the first thread, and responsive to the detection of the flow marker, a thread switching operation is performed with respect to the output of the instruction streaming buffer. The dispatch of instruction information of a second thread from the instruction streaming buffer is thus commenced.
    Type: Grant
    Filed: September 20, 2002
    Date of Patent: February 8, 2005
    Assignee: Intel Corporation
    Inventors: Stavros Kalafatis, Alan B. Kyker, Robert D. Fisch
  • Patent number: 6850961
    Abstract: A method of performing a thread switching operation within a multithreaded processor includes detecting dispatch of a first predetermined quantity of instruction information of a first thread, from an instruction streaming buffer to an instruction pre-decoder within the multithreaded processor. A stall condition relating to the first thread within a processor pipeline of the multithreaded processor is detected. The elapsing of a predetermined time interval subsequent to the detection of the stall condition is also detected. Responsive to the detection of the dispatch of the first predetermined quantity of instruction information for the first thread and the elapsing of the predetermined time interval, a thread switching operation is performed with respect to the output of the instruction streaming buffer.
    Type: Grant
    Filed: September 20, 2002
    Date of Patent: February 1, 2005
    Assignee: Intel Corporation
    Inventors: Stavros Kalafatis, Alan B. Kyker, Robert D. Fisch
  • Patent number: 6795845
    Abstract: A method of performing a thread switching operation within a multithreaded processor includes detecting dispatch of a first predetermined quantity of instruction information of a first thread, from an instruction streaming buffer to an instruction pre-decoder within the multithreaded processor. A branch instruction within the instruction information of the first thread to be dispatched from the instruction information source is also detected. Responsive to the detection of the branch instruction and the detection of the dispatch of the first predetermined quantity of instruction information of the first thread, a thread switching operation is performed with respect to the output of the instruction streaming buffer. The dispatch of instruction information of a second thread from the instruction streaming buffer is thus commenced.
    Type: Grant
    Filed: September 20, 2002
    Date of Patent: September 21, 2004
    Assignee: Intel Corporation
    Inventors: Stavros Kalafatis, Alan B. Kyker, Robert D. Fisch
  • Patent number: 6785890
    Abstract: A method of performing a thread switching operation within a multithreaded processor includes detecting the dispatch of a first predetermined quantity of instruction information of a first thread, from an instruction streaming buffer to an instruction pre-decoder within the multithreaded processor. An absence of a flow of instruction information of the first thread into the instruction information source from an upstream source in a processor pipeline is detected. The elapsing of a predetermined time interval subsequent to the detection of the absence of the flow of the instruction information is also detected. Responsive to the detection of the dispatch of the first predetermined quantity of instruction information of the first thread, and responsive to the elapsing of the predetermined time interval, a thread switching operation is performed with respect to the output of the instruction streaming buffer.
    Type: Grant
    Filed: September 20, 2002
    Date of Patent: August 31, 2004
    Assignee: Intel Corporation
    Inventors: Stavros Kalafatis, Alan B. Kyker, Robert D. Fisch
  • Patent number: 6535905
    Abstract: A method of performing a thread switching operation within a multithreaded processor. The dispatch of a first predetermined quantity of instruction information for a first thread, from an instruction streaming buffer to an instruction pre-decoder within the multithreaded processor, is detected. Responsive to the detection of the dispatch of the first predetermined quantity of instruction information for the first thread, a thread switching operation is performed with respect to the output of the instruction streaming buffer. The dispatch of instruction information for a second thread from the instruction streaming buffer is thus commenced. The utilization of processor resources is distributed between threads according to the quantity of instruction data for a particular thread that has been processed (or dispatch for processing), and not according to an arbitrary timing mechanism.
    Type: Grant
    Filed: April 29, 1999
    Date of Patent: March 18, 2003
    Assignee: Intel Corporation
    Inventors: Stavros Kalafatis, Alan B. Kyker, Robert D. Fisch
  • Publication number: 20030023834
    Abstract: A method of performing a thread switching operation within a multithreaded processor includes detecting the dispatch of a first predetermined quantity of instruction information of a first thread, from an instruction streaming buffer to an instruction pre-decoder within the multithreaded processor. Responsive to the detection of the dispatch of the first predetermined quantity of instruction information of the first thread, a thread switching operation is performed with respect to the output of the instruction streaming buffer. A flow marker is inserted into an instruction stream, the instruction stream including the instruction information of the first thread dispatched from the instruction information source, and the flow marker indicating that the thread switching operation has occurred. The dispatch of instruction information for a second thread from the instruction streaming buffer is thus commenced.
    Type: Application
    Filed: September 20, 2002
    Publication date: January 30, 2003
    Inventors: Stavros Kalafatis, Alan B. Kyker, Robert D. Fisch
  • Publication number: 20030023658
    Abstract: A method of performing a thread switching operation within a multithreaded processor includes detecting the dispatch of a first predetermined quantity of instruction information of a first thread, from an instruction streaming buffer to an instruction pre-decoder within the multithreaded processor. An absence of a flow of instruction information of the first thread into the instruction information source from an upstream source in a processor pipeline is detected. The elapsing of a predetermined time interval subsequent to the detection of the absence of the flow of the instruction information is also detected. Responsive to the detection of the dispatch of the first predetermined quantity of instruction information of the first thread, and responsive to the elapsing of the predetermined time interval, a thread switching operation is performed with respect to the output of the instruction streaming buffer.
    Type: Application
    Filed: September 20, 2002
    Publication date: January 30, 2003
    Inventors: Stavros Kalafatis, Alan B. Kyker, Robert D. Fisch
  • Publication number: 20030023659
    Abstract: A method of performing a thread switching operation within a multithreaded processor. The dispatch of a first predetermined quantity of instruction information for a first thread, from an instruction streaming buffer to an instruction pre-decoder within the multithreaded processor, is detected. Responsive to the detection of the dispatch of the first predetermined quantity of instruction information for the first thread, a thread switching operation is performed with respect to the output of the instruction streaming buffer. The dispatch of instruction information for a second thread from the instruction streaming buffer is thus commenced. The utilization of processor resources is distributed between threads according to the quantity of instruction data for a particular thread that has been processed (or dispatch for processing), and not according to an arbitrary timing mechanism.
    Type: Application
    Filed: September 20, 2002
    Publication date: January 30, 2003
    Inventors: Stavros Kalafatis, Alan B. Kyker, Robert D. Fisch
  • Publication number: 20030023835
    Abstract: A method of performing a thread switching operation within a multithreaded processor includes detecting dispatch of a first predetermined quantity of instruction information of a first thread, from an instruction streaming buffer to an instruction pre-decoder within the multithreaded processor. Responsive to the detection of the dispatch of the first predetermined quantity of instruction information for the first thread, a thread switching operation is performed with respect to the output of the instruction streaming buffer. The dispatch of instruction information for a second thread from the instruction streaming buffer is thus commenced. The predetermined quantity of the instruction information may be equal to or greater than a minimum quantity of instruction information for a full instruction of a first instruction set.
    Type: Application
    Filed: September 20, 2002
    Publication date: January 30, 2003
    Inventors: Stavros Kalafatis, Alan B. Kyker, Robert D. Fisch
  • Publication number: 20030018685
    Abstract: A method of performing a thread switching operation within a multithreaded processor includes detecting dispatch of a first predetermined quantity of instruction information of a first thread, from an instruction streaming buffer to an instruction pre-decoder within the multithreaded processor. A branch instruction within the instruction information of the first thread to be dispatched from the instruction information source is also detected. Responsive to the detection of the branch instruction and the detection of the dispatch of the first predetermined quantity of instruction information of the first thread, a thread switching operation is performed with respect to the output of the instruction streaming buffer. The dispatch of instruction information of a second thread from the instruction streaming buffer is thus commenced.
    Type: Application
    Filed: September 20, 2002
    Publication date: January 23, 2003
    Inventors: Stavros Kalafatis, Alan B. Kyker, Robert D. Fisch
  • Publication number: 20030018687
    Abstract: A method of performing a thread switching operation within a multithreaded processor includes detecting dispatch of a first predetermined quantity of instruction information of a first thread, from an instruction streaming buffer to an instruction pre-decoder within the multithreaded processor. A flow marker within instruction information for the first thread received at the instruction information source is also detected. Responsive to the detection of the dispatch of the first predetermined quantity of instruction information of the first thread, and responsive to the detection of the flow marker, a thread switching operation is performed with respect to the output of the instruction streaming buffer. The dispatch of instruction information of a second thread from the instruction streaming buffer is thus commenced.
    Type: Application
    Filed: September 20, 2002
    Publication date: January 23, 2003
    Inventors: Stavros Kalafatis, Alan B. Kyker, Robert D. Fisch
  • Publication number: 20030018686
    Abstract: A method of performing a thread switching operation within a multithreaded processor includes detecting dispatch of a first predetermined quantity of instruction information of a first thread, from an instruction streaming buffer to an instruction pre-decoder within the multithreaded processor. A stall condition relating to the first thread within a processor pipeline of the multithreaded processor is detected. The elapsing of a predetermined time interval subsequent to the detection of the stall condition is also detected. Responsive to the detection of the dispatch of the first predetermined quantity of instruction information for the first thread and the elapsing of the predetermined time interval, a thread switching operation is performed with respect to the output of the instruction streaming buffer.
    Type: Application
    Filed: September 20, 2002
    Publication date: January 23, 2003
    Inventors: Stavros Kalafatis, Alan B. Kyker, Robert D. Fisch