Patents by Inventor Robert D. Herzl

Robert D. Herzl has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11221957
    Abstract: A method, computer program product, and a computer system are disclosed for processing information in a processor that in one or more embodiments includes receiving a request for an Effective Address to Real Address Translation (ERAT); determining whether there is a permissions miss; changing, in response to determining there is a permission miss, permissions of an ERAT cache entry; and providing a Real Address translation. The method, computer program product, and computer system may optionally include providing a promote checkout request to a memory management unit (MMU).
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: January 11, 2022
    Assignee: International Business Machines Corporation
    Inventors: Bartholomew Blaner, Jay G. Heaslip, Benjamin Herrenschmidt, Robert D. Herzl, Jody Joyner, Jon K. Kriegel, Charles D. Wait
  • Patent number: 10884943
    Abstract: A method, computer program product, and a computer system are disclosed for processing information in a processor that in one or more embodiments includes setting a threshold number of free Effective to Real Address Translation (ERAT) cache entries in an ERAT cache; determining whether a total number of free ERAT cache entries is less than or equal to the threshold number of free ERAT cache entries; allocating, in response to determining that the total number of free entries is less than or equal to the threshold number, one or more active ERAT cache entries to be speculatively checked in to a memory management unit (MMU); and speculatively checking in the one or more active ERAT cache entries to the MMU.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: January 5, 2021
    Assignee: International Business Machines Corporation
    Inventors: Bartholomew Blaner, Jay G. Heaslip, Robert D. Herzl, Jody B. Joyner, Jeffrey A. Stuecheli
  • Patent number: 10599569
    Abstract: A technique for operating a memory management unit (MMU) of a processor includes the MMU detecting that one or more address translation invalidation requests are indicated for an accelerator unit (AU). In response to detecting that the invalidation requests are indicated, the MMU issues a raise barrier request for the AU. In response to detecting a raise barrier response from the AU to the raise barrier request the MMU issues the invalidation requests to the AU. In response to detecting an address translation invalidation response from the AU to each of the invalidation requests, the MMU issues a lower barrier request to the AU. In response to detecting a lower barrier response from the AU to the lower barrier request, the MMU resumes handling address translation check-in and check-out requests received from the AU.
    Type: Grant
    Filed: June 23, 2016
    Date of Patent: March 24, 2020
    Assignee: International Business Machines Corporation
    Inventors: Bartholomew Blaner, Jay G. Heaslip, Robert D. Herzl, Jody B. Joyner
  • Publication number: 20200073817
    Abstract: A method, computer program product, and a computer system are disclosed for processing information in a processor that in one or more embodiments includes receiving a request for an Effective Address to Real Address Translation (ERAT); determining whether there is a permissions miss; changing, in response to determining there is a permission miss, permissions of an ERAT cache entry; and providing a Real Address translation. The method, computer program product, and computer system may optionally include providing a promote checkout request to a memory management unit (MMU).
    Type: Application
    Filed: August 31, 2018
    Publication date: March 5, 2020
    Inventors: Bartholomew Blaner, Jay G. Heaslip, Benjamin Herrenschmidt, Robert D. Herzl, Jody Joyner, Jon K. Kriegel, Charles D. Wait
  • Publication number: 20200073816
    Abstract: A method, computer program product, and a computer system are disclosed for processing information in a processor that in one or more embodiments includes setting a threshold number of free Effective to Real Address Translation (ERAT) cache entries in an ERAT cache; determining whether a total number of free ERAT cache entries is less than or equal to the threshold number of free ERAT cache entries; allocating, in response to determining that the total number of free entries is less than or equal to the threshold number, one or more active ERAT cache entries to be speculatively checked in to a memory management unit (MMU); and speculatively checking in the one or more active ERAT cache entries to the MMU.
    Type: Application
    Filed: August 30, 2018
    Publication date: March 5, 2020
    Applicants: International Business Machines Corporation, International Business Machines Corporation
    Inventors: Bartholomew Blaner, Jay G. Heaslip, Robert D. Herzl, Jody B. Joyner, Jeffrey A. Stuecheli
  • Patent number: 10169500
    Abstract: Embodiments of the invention provide a method, system, and program product for predicting a delay of a critical path. In one embodiment, the invention provides a method of predicting a delay of at least one critical path of an integrated circuit, the method comprising: determining a delay of at least one ring oscillator on the integrated circuit; and calculating a predicted delay for the at least one critical path delay based on a delay of components of the critical path at a corner condition, a wire delay of the at least one critical path, a delay of the at least one ring oscillator at a corner condition, and the determined delay of the at least one ring oscillator.
    Type: Grant
    Filed: August 8, 2011
    Date of Patent: January 1, 2019
    Assignee: International Business Machines Corporation
    Inventors: Margaret R. Charlebois, Rashmi D. Chatty, Christopher D. Hanudel, Robert D. Herzl, David W. Milton, Clarence R. Ogilvie, Matthew P. Szafir, Tad J. Wilder
  • Patent number: 10006964
    Abstract: Disclosed are a chip performance monitoring system, method and a computer program product, wherein a performance monitor output signal is propagated through an adjacent scan chain to avoid signal degradation incident to across-chip transmission of high frequency signals. Since the clock signal frequency used to control signal propagation through the scan chain will typically be less than twice the performance monitor output signal frequency, frequency sub-sampling with aliasing occurs. To compensate, signal propagation through the scan chain can be controlled during different time periods using different clock signals having different clock signal frequencies and, during these different time periods, different data outputs can be captured at an output node of the scan chain. The data output frequencies of these different data outputs can be measured and the performance monitor output signal frequency can be determined based on the different data output frequencies given the different clock signal frequencies.
    Type: Grant
    Filed: April 21, 2016
    Date of Patent: June 26, 2018
    Assignee: International Business Machines Corporation
    Inventors: Margaret R. Charlebois, Christopher D. Hanudel, Robert D. Herzl, David W. Milton, Clarence R. Ogilvie, Paul M. Schanely, Tad J. Wilder
  • Publication number: 20170371789
    Abstract: A technique for operating a memory management unit (MMU) of a processor includes the MMU detecting that one or more address translation invalidation requests are indicated for an accelerator unit (AU). In response to detecting that the invalidation requests are indicated, the MMU issues a raise barrier request for the AU. In response to detecting a raise barrier response from the AU to the raise barrier request the MMU issues the invalidation requests to the AU. In response to detecting an address translation invalidation response from the AU to each of the invalidation requests, the MMU issues a lower barrier request to the AU. In response to detecting a lower barrier response from the AU to the lower barrier request, the MMU resumes handling address translation check-in and check-out requests received from the AU.
    Type: Application
    Filed: June 23, 2016
    Publication date: December 28, 2017
    Inventors: BARTHOLOMEW BLANER, JAY G. HEASLIP, ROBERT D. HERZL, JODY B. JOYNER
  • Publication number: 20160231379
    Abstract: Disclosed are a chip performance monitoring system, method and a computer program product, wherein a performance monitor output signal is propagated through an adjacent scan chain to avoid signal degradation incident to across-chip transmission of high frequency signals. Since the clock signal frequency used to control signal propagation through the scan chain will typically be less than twice the performance monitor output signal frequency, frequency sub-sampling with aliasing occurs. To compensate, signal propagation through the scan chain can be controlled during different time periods using different clock signals having different clock signal frequencies and, during these different time periods, different data outputs can be captured at an output node of the scan chain. The data output frequencies of these different data outputs can be measured and the performance monitor output signal frequency can be determined based on the different data output frequencies given the different clock signal frequencies.
    Type: Application
    Filed: April 21, 2016
    Publication date: August 11, 2016
    Applicant: International Business Machines Corporation
    Inventors: Margaret R. Charlebois, Christopher D. Hanudel, Robert D. Herzl, David W. Milton, Clarence R. Ogilvie, Paul M. Schanely, Tad J. Wilder
  • Patent number: 9383766
    Abstract: Disclosed are a chip performance monitoring system, method and a computer program product, wherein a performance monitor output signal is propagated through an adjacent scan chain to avoid signal degradation incident to across-chip transmission of high frequency signals. Since the clock signal frequency used to control signal propagation through the scan chain will typically be less than twice the performance monitor output signal frequency, frequency sub-sampling with aliasing occurs. To compensate, signal propagation through the scan chain can be controlled during different time periods using different clock signals having different clock signal frequencies and, during these different time periods, different data outputs can be captured at an output node of the scan chain. The data output frequencies of these different data outputs can be measured and the performance monitor output signal frequency can be determined based on the different data output frequencies given the different clock signal frequencies.
    Type: Grant
    Filed: January 9, 2013
    Date of Patent: July 5, 2016
    Assignee: International Business Machines Corporation
    Inventors: Margaret R. Charlebois, Christopher D. Hanudel, Robert D. Herzl, David W. Milton, Clarence R. Ogilvie, Paul M. Schanely, Tad J. Wilder
  • Patent number: 9188643
    Abstract: Aspects of the invention provide for a flexible performance screen ring oscillator (PSRO) integrated within a scan chain. In one embodiment, a circuit structure to create the flexible PSRO includes: a plurality of programmable scan chain elements; and a forward test scan chain path through the plurality of scan chain elements; wherein each of the programmable scan chain elements includes additional circuitry for a backward path, such that the backward path and the forward test scan chain path are combined to create the PSRO.
    Type: Grant
    Filed: November 13, 2012
    Date of Patent: November 17, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Margaret R. Charlebois, Christopher D. Hanudel, Robert D. Herzl, David W. Milton, Clarence R. Ogilvie, Paul M. Schanely, Tad J. Wilder
  • Patent number: 9128151
    Abstract: A performance screen ring oscillator (PSRO) formed from paired scan chains is disclosed. A circuit structure comprises scan chains each having scan chain elements. A scan chain link is configured to pair at least one scan chain element from a first scan chain with at least one scan chain element of a second scan chain to form a PSRO. A forward path associated with data flow through the at least one scan chain element of the first scan chain becomes a backward path of the at least one scan chain element of the second scan chain, and a forward path associated with data flow through the at least one scan chain element of the second scan chain becomes a backward path of the at least one scan chain element of the first scan chain.
    Type: Grant
    Filed: May 8, 2014
    Date of Patent: September 8, 2015
    Assignee: International Business Machines Corporation
    Inventors: Margaret R. Charlebois, Christopher D. Hanudel, Robert D. Herzl, David W. Milton, Clarence R. Ogilvie, Paul M. Schanely, Tad J. Wilder
  • Patent number: 9097765
    Abstract: A performance screen ring oscillator (PSRO) is formed from multi-dimensional pairings of scan chains. In one embodiment, there is a multi-dimensional arrangement of scan chains in an integrated circuit. Each of the scan chains has interconnected scan chain elements that form a shift register to apply test patterns to inputs of combinational logic in the integrated circuit and read outputs from the combinational logic based on the inputted test patterns. A scan chain link links selected scan chain elements from the scan chains to form at least one PSRO loop within the multi-dimensional arrangement of the scan chains.
    Type: Grant
    Filed: May 8, 2014
    Date of Patent: August 4, 2015
    Assignee: International Business Machines Corporation
    Inventors: Margaret R. Charlebois, Christopher D. Hanudel, Robert D. Herzl, David W. Milton, Clarence R. Ogilvie, Paul M. Schanely, Tad J. Wilder
  • Publication number: 20140195196
    Abstract: Disclosed are a chip performance monitoring system, method and a computer program product, wherein a performance monitor output signal is propagated through an adjacent scan chain to avoid signal degradation incident to across-chip transmission of high frequency signals. Since the clock signal frequency used to control signal propagation through the scan chain will typically be less than twice the performance monitor output signal frequency, frequency sub-sampling with aliasing occurs. To compensate, signal propagation through the scan chain can be controlled during different time periods using different clock signals having different clock signal frequencies and, during these different time periods, different data outputs can be captured at an output node of the scan chain. The data output frequencies of these different data outputs can be measured and the performance monitor output signal frequency can be determined based on the different data output frequencies given the different clock signal frequencies.
    Type: Application
    Filed: January 9, 2013
    Publication date: July 10, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Margaret R. Charlebois, Christopher D. Hanudel, Robert D. Herzl, David W. Milton, Clarence R. Ogilvie, Paul M. Schanely, Tad J. Wilder
  • Patent number: 8754696
    Abstract: Aspects of the invention provide a circuit structure that automatically monitors a plurality of ring oscillators and dynamically selects the fastest or the slowest ring oscillator for feedback into the plurality of ring oscillators. In one embodiment, a circuit includes: a plurality of delay elements, each delay element associated with a ring oscillator; a first logic gate for receiving outputs of each of the delay elements; a second logic gate for receiving outputs of each of the delay elements; and a multiplexer for receiving an output of the first logic gate and an output of the second logic gate and choosing one of the outputs, wherein a selection for the multiplexer is based on an output of the multiplexer. To select the fastest ring oscillator, a second multiplexer is provided.
    Type: Grant
    Filed: July 26, 2012
    Date of Patent: June 17, 2014
    Assignee: International Business Machines Corporation
    Inventors: Margaret R. Charlebois, Rashmi D. Chatty, Christopher D. Hanudel, Robert D. Herzl, David W. Milton, Clarence R. Ogilvie, Paul M. Schanely, Matthew P. Szafir, Tad J. Wilder
  • Publication number: 20140132290
    Abstract: Aspects of the invention provide for a flexible performance screen ring oscillator (PSRO) integrated within a scan chain. In one embodiment, a circuit structure to create the flexible PSRO includes: a plurality of programmable scan chain elements; and a forward test scan chain path through the plurality of scan chain elements; wherein each of the programmable scan chain elements includes additional circuitry for a backward path, such that the backward path and the forward test scan chain path are combined to create the PSRO.
    Type: Application
    Filed: November 13, 2012
    Publication date: May 15, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Margaret R. Charlebois, Christopher D. Hanudel, Robert D. Herzl, David W. Milton, Clarence R. Ogilvie, Paul M. Schanely, Tad J. Wilder
  • Patent number: 8667223
    Abstract: A cache for use in a central processing unit (CPU) of a computer includes a data array; a tag array configured to hold a list of addresses corresponding to each data entry held in the data array; a least recently used (LRU) array configured to hold data indicating least recently used data entries in the data array; a line fill buffer configured to receive data from an address in main memory that is located external to the cache in the event of a cache miss; and a shadow register associated with the line fill buffer, wherein the shadow register is configured to hold LRU data indicating a current state of the LRU array.
    Type: Grant
    Filed: August 11, 2011
    Date of Patent: March 4, 2014
    Assignee: International Business Machines Corporation
    Inventors: Thomas B. Chadwick, Jr., Robert D. Herzl, Kenneth A. Lauricella, Arnold S. Tran
  • Publication number: 20140028365
    Abstract: Aspects of the invention provide a circuit structure that automatically monitors a plurality of ring oscillators and dynamically selects the fastest or the slowest ring oscillator for feedback into the plurality of ring oscillators. In one embodiment, a circuit includes: a plurality of delay elements, each delay element associated with a ring oscillator; a first logic gate for receiving outputs of each of the delay elements; a second logic gate for receiving outputs of each of the delay elements; and a multiplexer for receiving an output of the first logic gate and an output of the second logic gate and choosing one of the outputs, wherein a selection for the multiplexer is based on an output of the multiplexer. To select the fastest ring oscillator, a second multiplexer is provided.
    Type: Application
    Filed: July 26, 2012
    Publication date: January 30, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Margaret R. Charlebois, Rashmi D. Chatty, Christopher D. Hanudel, Robert D. Herzl, David W. Milton, Clarence R. Ogilvie, Paul M. Schanely, Matthew P. Szafir, Tad J. Wilder
  • Patent number: 8464199
    Abstract: A method for designing an integrated circuit. A computer determines, for one or more paths in a circuit design, for a value of a design variable at which timing closure of the circuit design is achieved, an approximate slope of a function representing path delay as a function of the design variable. When the computer determines that one of the approximate slopes is not within a defined slope range, the computer determines an adjustment direction and an adjustment value based in part on the magnitude by which the slope is not within the defined slope range. The computer changes the circuit design of the path associated with the out-of-range slope, based in part on the adjustment direction and the adjustment value, so as to bring the slope within the defined slope range.
    Type: Grant
    Filed: May 16, 2012
    Date of Patent: June 11, 2013
    Assignee: International Business Machines Corporation
    Inventors: Margaret R. Charlebois, Christopher D. Hanudel, Robert D. Herzl, David W. Milton, Clarence R. Ogilvie, Paul M. Schanely, Tad J. Wilder
  • Publication number: 20130041608
    Abstract: Embodiments of the invention provide a method, system, and program product for predicting a delay of a critical path. In one embodiment, the invention provides a method of predicting a delay of at least one critical path of an integrated circuit, the method comprising: determining a delay of at least one ring oscillator on the integrated circuit; and calculating a predicted delay for the at least one critical path delay based on a delay of components of the critical path at a corner condition, a wire delay of the at least one critical path, a delay of the at least one ring oscillator at a corner condition, and the determined delay of the at least one ring oscillator.
    Type: Application
    Filed: August 8, 2011
    Publication date: February 14, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Margaret R. Charlebois, Rashmi D. Chatty, Christopher D. Hanudel, Robert D. Herzl, David W. Milton, Clarence R. Ogilvie, Matthew P. Szafir, Tad J. Wilder