Abstract: An ATM switch is configured to route ATM traffic from two receive circuits to a destination. One copy of this traffic is discarded in one of the receive circuits so that only a single copy is passed to the ATM switch. Receive circuits contemplate both virtual path (VP) level and card or circuit level metrics for qualification of signals.

Abstract: A TDM switch is configured to route TDM traffic from two receive circuits to a destination. One copy of the traffic is discarded, and a memory selectively stores the other copy for routing to the TDM switch. Receive circuits contemplate both virtual tributary (VT) level and card or circuit level metrics for qualification of signals.

Abstract: A method and system for distributed processing of traffic in a telecommunications node includes receiving a traffic stream at a line card of the telecommunications node. The traffic stream includes a plurality of discrete cells. The cells are forwarded from the line card to a centralized switch of the telecommunications node. The centralized switch identifies cells that are of a particular type. Cells of the particular type are returned from the centralized switch to the line card. The returned cells are processed at the line card.

Abstract: Errors in digital transmission are monitored by employing a cyclical-redundancy-check (CRC). A CRC code word having a predetermined number of bits is generated (via 310) from a block of bits (ESF) of a presently transmitted time division muliplexed (XTDM) signal. The code word bits are then inserted (via 304, 305, 306) into predetermined bit positions of the next subsequent block of bits (ESF) of the XTDM signal. In a receiver (FIG. 7), bits of a presently received time division multiplexed (RTDM) signal are compared (801, 802) to bits of a CRC code word generated from the last previously received block of bits to indicate errors in transmission. In a specific example, a 6-bit CRC code word is employed and the code word bits are inserted into predetermined framing bit positions.

Abstract: Framing of a digital receiver to synchronize with a true framing pattern is realized by employing an autonomous clock to generate framing pattern bits and other timing signal, and by employing a cyclical-redundancy-check (CRC) to eliminate the possibility of framing on false framing patterns. To this end, a frame synchronization circuit detects all possible framing candidate bit positions in a received time division signal and generates a frame resynchronization pulse corresponding to the framing candidate bit positions thereby causing the autonomous clock to synchronize to the associated framing pattern. If the framing pattern on which the clock is synchronized is a false one a loss of CRC signal is generated which initiates synchronizing on the next detected framing pattern. This process is iterated until no loss of CRC signal is generated thereby indicating synchronization on the true framing pattern.

Abstract: A digital data transmission rate of three bits per cycle of bandwidth is achieved in precoded partial-response band-limited communication channels by partitioning binary digits into groups of three two-level digits and translating these binary groups of three into pairs of three-level digits prior to transmission. Correct pairwise association of received signals is accomplished by reserving a three-level digit pair for monitoring purposes. This reserved pair can validly occur only at a transition between allowable pairs. By monitoring the presence of the reserved pair, correct pairwise association of ternary digits is assured and binary digits are properly decoded without having to provide a special framing signal.

Abstract: Errors in digital transmission are monitored by employing a cyclical-redundancy-check (CRC). A CRC code word having a predetermined number of bits is generated (via 310) from a block of bits (ESF) of a presently transmitted time division multiplexed (XTDM) signal. The code word bits are then inserted (via 304, 305, 306) into predetermined bit positions of the next subsequent block of bits (ESF) of the XTDM signal. In a receiver (FIG. 7), bits of a presently received time division multiplexed (RTDM) signal are compared (801, 802) to bits of a CRC code word generated from the last previously received block of bits to indicate errors in transmission. In a specific example, a 6-bit CRC code word is employed and the code word bits are inserted into predetermined framing bit positions.