Patents by Inventor Robert D. LeVasseur

Robert D. LeVasseur has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5372515
    Abstract: An ESD protection subassembly for a conductively-case module having an electrical connector mounted thereon, uses a conductive shield shell member formed about the connector and connected to the module conductive case; the shell member has at least one conductive door member mounted thereon by associated hinge formations having spring-like mechanisms for urging the door members to close off an opening in the shell member whenever the module is not mated with an associated receptacle connector. A substantially complete conductive peripheral enclosure is thus formed for the module and its attached connector, whether the module is mounted in a larger assembly with its complementary connector actually mated with the module-mounted connector, or if the module has been removed from the rack assembly.
    Type: Grant
    Filed: June 10, 1993
    Date of Patent: December 13, 1994
    Assignee: Martin Marietta Corporation
    Inventors: Gary Miller, Robert D. LeVasseur
  • Patent number: 4963414
    Abstract: The heat sinking substrate herein disclosed is comprised of a core consisting of a rigid graphitic solid in which hexagonal graphite crystallites are bond together by coal tar pitch, the core being enclosed by two metallic face sheets having a coefficient of thermal expansion suited to the electronic packages it supports. The substrate is designed to be installed into a module with a printed wiring board on either side, the module being installed in parallel with other like modules into a chassis. The heat generated by the electronics is input over the face of the substrate and withdrawn by cooling in the walls of the chassis with which the substrates are in good thermal contact. The grain of the core is aligned for maximum thermal conduction along the path to the chassis walls. The substrate is of low weight, has a CTE matched to the supported electronic packages, high thermal conductance, and uses low cost materials.
    Type: Grant
    Filed: June 12, 1989
    Date of Patent: October 16, 1990
    Assignee: General Electric Company
    Inventors: Robert D. LeVasseur, Stephen A. McKeown