Abstract: A microprocessor operates at a rate dependent upon the interrupt source of a plurality of interrupt sources. The rate of power consumption by the microprocessor corresponds to the selected rate of instruction operation. A rate table accessed upon receipt of an interrupt stores a table of interrupt source to rate of instruction operation. The rate table may be a read only memory or a read/write memory loaded upon initiation of the microprocessor. The rate of microprocessor instruction operation may be set by frequency of an instruction clock or by a rate of instruction dispatch. For a superscalar microprocessor the rate of instruction operation may be set by setting a number of instructions dispatched per instruction cycle. On receiving an interrupt a rate number is pushed onto a rate stack. On return from the interrupt the rate stack is popped. The microprocessor operates at a rate corresponding to the rate number at a top of the rate stack.

Abstract: A microprocessor preemptively write-backs dirty entries of an internal cache. Each cache entry is checked once each predetermined time period to determine if the cache entry is dirty. If dirty, a write history is checked to determine if the cache entry is stale. If stale, the cache entry in preemptively written back to main memory and then marked as clean. The write history includes a count of the number of consecutive predetermined time periods during which there is no write to the cache entry. The cache entry is stale if the count exceeds a predetermined number. For each check of the write history the nonwrite count is incremented if the cache entry has been written to during the prior cycle and decremented if not. Alternatively, the nonwrite count is set to zero if the cache entry has been written to. The dirty cache entry may be marked as clean upon copying to the write-back buffer or, alternatively, when the write-back buffer writes the dirty cache entry to the main memory.

Abstract: An apparatus for controlling address alignment fault generation employing a recoded two bit structure. This alignment fault state circuit stores one of four states corresponding to whether the operating system permits address misalignment fault generation and whether the application program requests such address misalignment fault generation. The two latches each hold either a first state or a second state. Together the two latches have either a first combined state, a second combined state, a third combined state or a fourth combined state. The two latches have a recoded set of states such that receipt of at least one of the alignment check on instruction, the alignment check off instruction, the alignment mask permit instruction or the alignment mask prohibit instruction causes both latches to change state.

Abstract: This invention employs a token passing structure for controlling alignment fault generation. This alignment fault state circuit stores one of four states corresponding to whether the operating system permits address misalignment fault generation and whether the application program requests such address misalignment fault generation. If the token is present in a particular latch, then the corresponding state is active. If the token is absent, then the corresponding state is inactive. The presence of the token in a predetermined one of the four states causes a fault gate qualifier signal to be active permitting fault generation on address misalignment. Absence of the token from that state causes the fault gate qualifier signal to be inactive prohibiting fault generation on address misalignment. This structure efficiently implements address misalignment fault control by means of token location. Every token location is accessible at every privilege level.