Abstract: An architecture for capture and generation, and a set of methods for characterization, prediction, and classification of traffic in packet networks are disclosed. The architecture consists of a device that stores packet timing information and processes the data so that characterization, prediction, and classification algorithms can perform operations in real-time. A methodology is disclosed for real-time traffic analysis, characterization, prediction, and classification in packet networks. The methodology is based on the simultaneous aggregation of packet arrival times at different times scales. The traffic is represented at the synchronous carrier level by the arrival or non-arrival of a packet. The invention does not require knowledge about the information source, nor needs to decode the information contents of the packets. Only the arrival timing information is required. The invention provides a characterization of the traffic on packet networks suitable for a real-time implementation.

Abstract: Built-in current mode quiescent current monitoring circuitry is provided for measuring a circuit's or a subcircuit's quiescent current. Anomalously high quiescent current (Iddq) generally results as a consequence of a manufacturing defect. These defects include those not detected by tests generated using traditional fault models. The technique provided here is based upon generating a proportionally matched current to the circuit under test current by a control loop. The proportionally matched current is then sent to a comparator where it is compared to a reference current, the reference current representing an acceptable quiescent current level. The output of the comparator then indicates whether the quiescent current is above or below the reference current.