Abstract: A method of storing sensitive data by generating randomization values, transforming the sensitive data and the randomization values into a result, and storing separate portions of the result on at least two storage devices, such that the sensitive data cannot be disclosed if any one of the storage devices is compromised.

Abstract: A method for producing a chip is disclosed. A first step of the method may involve fabricating the chip only up to and including a first metal layer during a first manufacturing phase such that an input/output (I/O) region of the chip has a plurality of slots, where each of the slots has a plurality of first transistors. A second step of the method may involve designing a plurality of upper metal layers above the first metal layer in response to a custom design created after the first fabricating has started, the upper metal layers interconnecting a plurality of the first transistors to form a plurality of mixed-signal building block functions. A third step of the method may involve fabricating the chip to add the upper metal layers during a second manufacturing phase.

Abstract: An apparatus comprising an integrated circuit having (i) a number of regions each pre-diffused and configured to be metal-programmed and (ii) a plurality of pins configured to connect the integrated circuit to a socket. A logic portion may be implemented on the integrated circuit (i) configured to implement integrated circuit operations and (ii) having one or more I/O connections and one or more supply connections. A first group of the pre-diffused regions are metal-programmed and coupled to said I/O connections. A second group of the pre-diffused regions are metal-programmed and coupled to the supply connections.

Abstract: An apparatus including a base layer of a platform application specific integrated circuit (ASIC), a mixed-signal function and a built-in self test (BIST) function. The base layer of the platform ASIC generally includes a plurality of pre-diffused regions disposed around a periphery of the platform ASIC. Each of the pre-diffused regions is generally configured to be metal-programmable. The mixed-signal function may include two or more sub-functions formed with a metal mask set placed over a first number of the plurality of pre-diffused regions. The BIST function may be formed with a metal mask set placed over a second number of the plurality of pre-diffused regions. The BIST function may be configured to test the mixed-signal function and present a digital signal indicating an operating condition of the mixed-signal function.

Abstract: A method for producing a chip is disclosed. A first step of the method may include fabricating the chip only up to and including a first metal layer such that a core region of the chip has an array of cells, each of the cells having a plurality of transistors. A second step generally involves designing a plurality of upper metal layers above the first metal layer in response to a custom design created after the first fabricating has started, the upper metal layers interconnecting a plurality of the cells to form (i) a mixed-signal module and (ii) a digital module, the mixed signal module generating at least one analog signal and at least one digital signal. In a third step, the method may include fabricating the chip to add the upper metal layers.

Abstract: An apparatus that may include a base layer of a platform application specific integrated circuit (ASIC) and a mixed-signal function. The base layer of the platform application specific integrated circuit (ASIC) generally comprises a plurality of pre-diffused regions disposed around a periphery of the platform ASIC. Each of the pre-diffused regions may be configured to be metal-programmable. The mixed-signal function may include two or more sub-functions formed with a metal mask set placed over a number of the plurality of pre-diffused regions.

Abstract: A method for interconnecting sub-functions of metal-mask programmable functions that includes the steps of (A) forming a base layer of a platform application specific integrated circuit (ASIC) comprising a plurality of pre-diffused regions disposed around a periphery of the platform ASIC, (B) forming two or more sub-functions of a function with a metal mask set placed over a number of the plurality of pre-diffused regions of the platform application specific integrated circuit and (C) configuring one or more connection points in each of the two or more sub-functions such that interconnections between the two or more sub-functions are tool routable in a single layer. Each of the pre-diffused regions is configured to be metal-programmable.

Abstract: A method for concentric metal density power distribution is disclosed that reduces metal density and increases available area for routing clock and signal traces. A method of concentric metal density power distribution includes the steps of partitioning an area of standard cells in an integrated circuit chip into a plurality of power regions, forming a power boundary around each of the plurality of power regions, and forming a plurality of concentric straps in a metal layer of the integrated circuit chip wherein each of the plurality of concentric straps has a strap width that varies from a maximum strap width at a periphery of each of the plurality of power regions to a minimum strap width toward a center of each of the plurality of power regions.

Abstract: A single-edge triggered phase detector which provides high speed phase detection. The phase detector works on only a single edge of the clock and data signal, which can be either the rising or falling edge. Extracted control signals are latched for at least one half of a clock period or more to ensure full rail to rail swing.

Abstract: A data communication method and apparatus includes an integral bit error rate test system. The system is adapted to receive digital data signals to be transmitted over a communication link and includes a transmitter for transmitting the data signals onto the link. A test signal pattern generator generates a determinable pattern of digital bit test signals which are insertable into an input of the transmitter in place of the digital data signals. A receiver is coupled to the link for receiving the bit test signals and for comparing the received pattern of the bit test signals to the determinable pattern. The bit error rate is computed from the number of bit differences between the transmitted test signals and the determinable pattern.

Abstract: The present invention is a method for enhancing reaction rates when digesting chemical systems which form passivating layers. Particles are introduced into a digestion fluid bath. Digestion is allowed to proceed until passivating layers of digestion products have partially formed on the particles. The layers constitute a diffusion barrier to the digestion fluid and reduce the digestion rate. The particles are periodically conveyed through an ultrasonic beam to remove portions of the passivating layers. Thus, fresh surfaces of the particles are exposed to the digestion fluid bath. The periodic conveyance is such that a desired rate of digestion is obtained.

Abstract: A charge pump circuit for a phase-locked loop circuit which provides substantially constant charge and discharge currents characterized by minimal overshoots and undershoots. The charge pump circuit includes a level shifter circuit which attenuates voltage swings in Up and Down signals from the phase detector and provides control signals. The charge pump circuit also includes a feedback circuit coupled to the level shifter which compares the output voltage of the charge pump to predetermined first and second reference voltages and increases and decreases the charge and discharge currents to minimize overshoot and undershoot noise as determined by the control signals.

Abstract: A differential inverter such as may be used in an oscillator circuit. The differential inverter is connected between first and second current sources. The differential inverter includes first and second single signal CMOS inverters connected in parallel between the first and second controlled current sources. Each of the current sources is a MOS transistor. A bias circuit is connected to the control gates of the MOS transistors and provides bias signals thereto, the bias circuit includes a variable current source with bias signals being generated in response to the current flow in the variable current source.

Abstract: A device and method for approximating the square root of a binary number N. The device includes hardware for storing N, and a result register for storing x.sub.n, where x.sub.n is a successive approximation of r. The device also includes hardware for iteratively replacing x.sub.n with x.sub.n+1, starting with n=0, where x.sub.n+1 =(Ax.sub.n +N-x.sub.n.sup.2)/A, and x.sub.0 is within a predetermined range. "A" is a multiple of 2 so that an operation involving a product or quotient with "A" is effected by a shift operation.

Abstract: The system includes at least one electrolysis cell having a principal direction of current flow. The electrolysis cell has two electrode surfaces whose mean surface planes are substantially parallel, separated by a fluid electrolyte layer.Separate electric current conducting means, energized by an electric power source and independent of the electrolysis circuit elements are so arranged and constructed with respect to the cell to increase the average component of the magnetic field substantially parallel to the mean electrode surfaces within the fluid electrolyte layer. This increase in the magnetic field is relative to the magnetic field due solely to the electrolysis current. A flow return conduit is included for connecting at least one entrance port of the electrolysis cell to a least one exit port of the electrolysis cell. The ports are disposed substantially parallel to the pressure gradient formed by the magnetic forces present during operation.

Abstract: A voltage variable delay circuit that provides a relatively constant delay independent of operating voltages, temperatures or processing variations is disclosed. The circuit is particularly suited for delay line or oscillator applications. The relatively constant delay is accomplished by accurately controlling the switching speed of each of the complementary series arranged inverter elements used for the delay line or oscillator. The accurate control is provided by first and second high impedance inverters connected to the gate electrode of series arranged inverters. In the delay line application, two similarly fabricated series arranged inverter elements are placed in parallel. One of the series arranged inverters is used as an operating circuit and the other is used as a reference circuit. A clock signal is used to synchronize the reference circuit with a timing network, and a comparator is used to measure the time difference between the reference circuit and the timing network.

Abstract: A system for transmitting microwaves to one or more receiver assemblies comprises an array of separate microwave transmitting assemblies for emitting a plurality of microwave beams, the array being arranged to apparently fill a radiating aperture of predetermined shape and size when viewed from the direction of a receiver assembly, and a phase controlling assembly associated with the microwave transmitting assemblies for controlling the relative phase of the emitted beams to form at least one composite shaped microwave beam directed to at least one receiver assembly. The receiver assembly is located in the near field of the microwave beam. The transmitting assemblies are each associated with separate power sources comprising solar power collecting assemblies. In one arrangement the transmitting system is on the moon and the or each receiver assembly is on Earth.

Abstract: An electrical connection between a first bus and a second bus on a semiconductor integrated circuit device manufactured using conventional CMOS technology. The first bus has a horn shape which permits a plurality of vias to be arranged in an arc thereon. This arrangement of vias facilitates permitting the current to flow substantially evenly between a first bus and a second bus.

Abstract: A high speed, D-type flip-flop is implemented using eight complementary metal-oxide semiconductor (CMOS) tristate inverters. The flip-flop includes both D and D/ data input terminals and parallel data paths from the data input terminals to Q and Q/ output terminals. The improved circuit design realizes higher operating speed than prior CMOS flip-flops by eliminating the inverter delays present in single path flip-flops and providing only two gates in the data paths between the input and output terminals.

Abstract: A system for transmitting microwaves to one or more receiver assemblies comprises an array of separate microwave transmitting assemblies for emitting a plurality of microwave beams, the array being arranged to apparently fill a radiating aperture of predetermined shape and size when viewed from the direction of a receiver assembly, and a phase controlling assembly associated with the microwave transmitting assemblies for controlling the relative phase of the emitted beams to form at least one composite shaped microwave beam directed to at least one receiver assembly. The receiver assembly is located in the near field of the microwave beam. The transmitting assemblies are each associated with separate power sources comprising solar power collecting assemblies. In one arrangement the transmitting system is on the moon and the or each receiver assembly is on Earth.