Abstract: A color television receiver system processes color difference signals for providing tint control while maintaining uniform color amplitude with respect to changes in hue shift angle. The color difference signals are modified as a function of each other and as a function of a hue shift angle to produce modified color difference signals. A color difference signal [B-Y] is supplied as a first input to multipliers M1 and M3. Another color difference signal [R-Y] is supplied as a first input to another pair of multipliers M2 and M4. A control signal generator produces output signals sin ? and cos ? where ? is the hue shift angle. The sin ? signal is supplied as a second input to multipliers M1 and M4 while the cos ? signal is supplied as a second input to multipliers M2 and M3. The outputs of M1 and M2 are added in an adder A1 to produce a modified output [R-Y]?.

Abstract: A horizontal synchronizing system, comprising: a source of a horizontal synchronizing signal; a source of first and second higher frequency horizontal drive signals; a phase detector for generating a first control voltage responsive to the horizontal synchronizing signal and the first horizontal drive signal; a source of a second control signal; and, a switch for selectively supplying the first control signal to the source of the drive signals for a phase-locked mode of operation at the first higher frequency and supplying the second control signal to the source of the drive signals for a phase-unlocked mode of operation at the second higher frequency.

Abstract: A phase locked loop, comprising: a controllable oscillator requiring a control signal having a given bias voltage for generating a clock signal; an integrator for developing the control signal; a source of an external synchronizing signal; first and second voltage sources defining a voltage potential related to the given bias voltage; a first switch coupled to the first and second voltage sources and responsive to the clock signal for developing a regenerated clock signal having a peak to peak voltage determined by the voltage potential; and, a second switch responsive to the external synchronizing signal for periodically sampling portions of the regenerated clock signal and coupling the sampled portions to the integrator, the sampled portions charging and discharging the integrator to generate the control signal with a large enough magnitude to provide the given bias voltage, said first and second switches forming a phase detector.

Abstract: A phase locked loop, comprising: a controllable oscillator requiring a control signal having a given bias voltage for generating a clock signal; an integrator for developing the control signal; a source of an external synchronizing signal; first and second voltage sources defining a voltage potential related to the given bias voltage; a first switch coupled to the first and second voltage sources and responsive to the clock signal for developing a regenerated clock signal having a peak to peak voltage determined by the voltage potential; and, a second switch responsive to the external synchronizing signal for periodically sampling portions of the regenerated clock signal and coupling the sampled portions to the integrator, the sampled portions charging and discharging the integrator to generate the control signal with a large enough magnitude to provide the given bias voltage, said first and second switches forming a phase detector.