Patents by Inventor Robert Daniel Edwards

Robert Daniel Edwards has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Edge seal for thru-silicon-via technology
    Patent number: 7919834
    Abstract: One or more multilayer back side metallurgy (BSM) stack structures are formed on thru-silicon-vias (TSV). The multiple layers of metal may include an adhesion layer of chromium on the semiconductor wafer back side, a conductive layer of copper, diffusion barrier layer of nickel and a layer of nobel metal, such as, gold. To prevent edge attack of copper after dicing, the layer of nickel is formed to seal the copper edge. To also prevent edge attack of the layer of nickel after dicing, the layer of gold is formed to seal both the layer of copper and the layer of nickel.
    Type: Grant
    Filed: December 4, 2007
    Date of Patent: April 5, 2011
    Assignee: International Business Machines Corporation
    Inventors: Robert Edgar Davis, Robert Daniel Edwards, J. Edwin Hostetter, Jr., Ping-Chuan Wang, Kimball M. Watson
  • EDGE SEAL FOR THRU-SILICON-VIA TECHNOLOGY
    Publication number: 20090140395
    Abstract: One or more multilayer back side metallurgy (BSM) stack structures are formed on thru-silicon-vias (TSV). The multiple layers of metal may include an adhesion layer of chromium on the semiconductor wafer back side, a conductive layer of copper, diffusion barrier layer of nickel and a layer of nobel metal, such as, gold. To prevent edge attack of copper after dicing, the layer of nickel is formed to seal the copper edge. To also prevent edge attack of the layer of nickel after dicing, the layer of gold is formed to seal both the layer of copper and the layer of nickel.
    Type: Application
    Filed: December 4, 2007
    Publication date: June 4, 2009
    Applicant: International Business Machines Corporation
    Inventors: Robert Edgar Davis, Robert Daniel Edwards, J. Edwin Hostetter, JR., Ping-Chuan Wang, Kimball M. Watson
  • Multiple material stacks with a stress relief layer between a metal structure and a passivation layer
    Publication number: 20020163062
    Abstract: A structure/method for reducing the stress between a dielectric, passivation layer and a metallic structure comprising coating the metallic structure with a low stress modulus buffer material, and forming the dielectric passivation layer covering the low stress modulus buffer material. The low stress modulus buffer material is composed of a layer of a polymeric material selected from at least one of the group consisting of a hydrogen/alkane SQ (SilsesQuioxane) resin, polyimide, and a polymer resin. The dielectric, passivation layer is composed of at least one layer of a material selected from at least one of the group consisting of silicon oxide and silicon nitride. A protective layer is formed over the dielectric, passivation layer. The low stress modulus buffer material has a thermal coefficient of expansion between that of the metallic structure and that of the dielectric passivation layer.
    Type: Application
    Filed: February 26, 2001
    Publication date: November 7, 2002
    Applicant: International Business Machines Corporation
    Inventors: Ping-Chuan Wang, Robert Daniel Edwards, John C. Malinowski, Vidhya Ramachandran, Steffen Kaldor
  • High temperature electromigration stress test system, test socket, and use thereof
    Patent number: 5760595
    Abstract: A test socket is provided as part of a high temperature electromigration test system to allow the prediction of median time to failure to temperatures in excess of 450.degree. C. of VSLI interconnects.
    Type: Grant
    Filed: September 19, 1996
    Date of Patent: June 2, 1998
    Assignee: International Business Machines Corporation
    Inventors: Robert Daniel Edwards, Du Binh Nguyen, James Joseph Poulin, Hazara Singh Rathore, Richard George Smith