Abstract: Binnable time-of-flight (ToF) pixels are described, such as for integration with image sensor pixels. Each binnable ToF pixel includes a central dump gate and sub-pixels that are nominally mirror-symmetric and identical around the dump gate. Each sub-pixel includes a photodiode region (or a respective portion of a photodiode region), a storage gate, a storage region, a transfer gate, and a floating diffusion (FD) region. In an array, the binnable ToF pixels are arranged to share FD regions with other binnable ToF pixels of the array. In an un-binned mode, each sub-pixel can integrate photocharge in its storage region until it is time for readout, at which time the photocharges can be transferred to its respective floating diffusion region for individualized readout. In a binned mode, sub-pixels can integrate photocharge directly in their FD regions, which facilitates charge binning of integrated photocharge from all sub-pixels sharing the same FD region.

Abstract: Binnable time-of-flight (ToF) pixels are described, such as for integration with image sensor pixels. Each binnable ToF pixel includes a central dump gate and sub-pixels that are nominally mirror-symmetric and identical around the dump gate. Each sub-pixel includes a photodiode region (or a respective portion of a photodiode region), a storage gate, a storage region, a transfer gate, and a floating diffusion (FD) region. In an array, the binnable ToF pixels are arranged to share FD regions with other binnable ToF pixels of the array. In an un-binned mode, each sub-pixel can integrate photocharge in its storage region until it is time for readout, at which time the photocharges can be transferred to its respective floating diffusion region for individualized readout. In a binned mode, sub-pixels can integrate photocharge directly in their FD regions, which facilitates charge binning of integrated photocharge from all sub-pixels sharing the same FD region.

Abstract: A pixel, is provided the pixel comprising: a photodiode structure built on top of an integrated circuit generating a charge; the integrated circuit comprising at least one semiconductor material and at least one interconnect layer; the at least one interconnect layer comprises an interconnect to facilitate charge flowing into a collection node disposed in the semiconductor material; the interconnect being in contact with a doped contact diffusion disposed proximate to the collection node; a transfer transistor disposed between the collection node and a conversion node, the conversion node coupled to an active transistor; the pixel having a reset configured to reset the conversion node.

Abstract: A uniform bridge gradient (UBG) time-of-flight (ToF) photodiode block is described, such as for integration with image sensor pixels. The UBG ToF photodiode block can be part of a UBG ToF pixel, and an image sensor can include an array of such pixels. Each UGB ToF photosensor block has multiple taps for selective activation, and a photodiode region designed for complete and rapid transit of photocarriers, as they are generated, via the multiple taps. Embodiments of the photodiode region include a photodiode-defining implant, a relatively shallow first bridging implant, and relatively deep second bridging implant. The bridging implants provide lateral bridging with a uniform doping gradient near and across the multiple taps.

Abstract: A system is provided for time delay integration in complementary metal oxide semiconductor imaging sensors, the system comprising: a two dimensional parallel charge transfer structure comprising at least one column of CMOS Image sensor pinned photodiodes; each the diode in the column being connected to the next the diode by a two phase transfer gate, each the transfer gate having a barrier and a well configured such that a flow of charge in the column is unidirectional.

Abstract: Devices and methods of minimizing the temporal error between pixels or groups of pixels on a focal plane array involving, on a focal plane array comprising at least two pixels or groups of pixels, at least one counter or ramp, and at least one trigger: determining the timing error associated with a time stamp associated with the at least two pixels or groups of pixels; storing the timing error associated with the at least two pixels or groups of pixels and the pixel or pixel group location; and using the stored timing error and pixel or pixel group location to correct subsequent time stamps associated with the at least two pixels or groups of pixels, wherein the timing error corresponds to a systematic error between the trigger and the counter or ramp value due to the location of a pixel or group of pixels on the focal plane array.

Abstract: Devices and methods of minimizing the temporal error between pixels or groups of pixels on a focal plane array involving, on a focal plane array comprising at least two pixels or groups of pixels, at least one counter or ramp, and at least one trigger: determining the timing error associated with a time stamp associated with the at least two pixels or groups of pixels; storing the timing error associated with the at least two pixels or groups of pixels and the pixel or pixel group location; and using the stored timing error and pixel or pixel group location to correct subsequent time stamps associated with the at least two pixels or groups of pixels, wherein the timing error corresponds to a systematic error between the trigger and the counter or ramp value due to the location of a pixel or group of pixels on the focal plane array.

Abstract: A pixel, is provided the pixel comprising: a photodiode structure built on top of an integrated circuit generating a charge; the integrated circuit comprising at least one semiconductor material and at least one interconnect layer; the at least one interconnect layer comprises an interconnect to facilitate charge flowing into a collection node disposed in the semiconductor material; the interconnect being in contact with a doped contact diffusion disposed proximate to the collection node; a transfer transistor disposed between the collection node and a conversion node, the conversion node coupled to an active transistor; the pixel having a reset configured to reset the conversion node.

Abstract: A pixel, is provided the pixel comprising: a photodiode structure built on top of an integrated circuit generating a charge; the integrated circuit comprising at least one semiconductor material and at least one interconnect layer; the at least one interconnect layer comprises an interconnect to facilitate charge flowing into a collection node disposed in the semiconductor material; the interconnect being in contact with a doped contact diffusion disposed proximate to the collection node; a transfer transistor disposed between the collection node and a conversion node, the conversion node coupled to an active transistor; the pixel having a reset configured to reset the conversion node.

Abstract: A system for low light level image sensing is provided having: A photodiode; a transfer gate disposed in a center of the photodiode; an active gate disposed surrounded by the transfer gate; a plurality of microlenses, each microlens being disposed over a portion of the photodiode and directing light away from the transfer gate towards the photodiode.

Abstract: A pixel, is provided the pixel comprising: a photodiode structure built on top of an integrated circuit generating a charge; the integrated circuit comprising at least one semiconductor material and at least one interconnect layer; the at least one interconnect layer comprises an interconnect to facilitate charge flowing into a collection node disposed in the semiconductor material; the interconnect being in contact with a doped contact diffusion disposed proximate to the collection node; a transfer transistor disposed between the collection node and a conversion node, the conversion node coupled to an active transistor; the pixel having a reset configured to reset the conversion node.

Abstract: A system for low light level image sensing is provided having: A photodiode; a transfer gate disposed in a center of the photodiode; an active gate disposed surrounded by the transfer gate; a plurality of microlenses, each microlens being disposed over a portion of the photodiode and directing light away from the transfer gate towards the photodiode

Abstract: Optical isolation is provided for optically black pixels in image sensors. Image sensors, such as backside illumination (BSI) image sensors, may have an active pixel array and an array having optically black pixels. Isolation structures such as a metal wall may be formed in a dielectric stack between an active pixel array and optically black pixels. Patterned shallow trench isolation regions or polysilicon regions may be formed in a substrate between an active pixel array and optically black pixels. An absorption region such as a germanium-doped absorption region may be formed in a substrate between an active pixel array and optically black pixels. Optical isolation and absorption regions may be formed in a ring surrounding an active pixel array.

Abstract: Optical isolation is provided for optically black pixels in image sensors. Image sensors, such as backside illumination (BSI) image sensors, may have an active pixel array and an array having optically black pixels. Isolation structures such as a metal wall may be formed in a dielectric stack between an active pixel array and optically black pixels. Patterned shallow trench isolation regions or polysilicon regions may be formed in a substrate between an active pixel array and optically black pixels. An absorption region such as a germanium-doped absorption region may be formed in a substrate between an active pixel array and optically black pixels. Optical isolation and absorption regions may be formed in a ring surrounding an active pixel array.

Abstract: An image sensing device comprising active pixels is disclosed, each pixel having a charge accumulation region for collecting charges generated by a photosensitive element such as a photodiode. A linear voltage to current converter, current mirrors, and a differential amplifier generate an output signal and minimize fixed pattern noise and improve the signal to noise ratio. Image quality is improved by reducing pixel blooming and image smearing through an improved method for resetting the pixels with a bias voltage reference which is less than Vdd. Active circuitry and physical device layout reduce the effects of IR voltage drops along the bus lines in a massive pixel array.

Abstract: An improved pixel design for a CMOS image sensor with a small feature size is described. In conventional image sensors of this type, the quantum efficiency is typically reduced as a result of the decreased thickness of the top n-type layer of the photodiode and the presence of an intervening p-type layer which is higher doped than the substrate. In the pixel design of the invention, the higher doped p-type layer underneath the photodiode is omitted while barrier regions channel the carriers generated by the impinging radiation towards the top n-layer of the photodiode. A high quantum efficiency is thereby attained in spite of a shrinking feature size. The novel pixel design can also incorporate anti-blooming protection.