Abstract: Embedded flush circuitry features are provided by providing a carrier foil having an electrically conductive layer therein and coating the electrically conductive layer with a dielectric material. Circuitry features are formed in the dielectric material and conductive metal is plated to fill the circuitry features.

Abstract: An electronic structure, and associated method of fabrication, that includes a substrate having attached circuit elements and conductive bonding pads of varying thickness. Pad categories relating to pad thickness include thick pads (17 to 50 microns), medium pads (10–17 microns), and thin pads (3 to 10 microns). A thick pad is used for coupling a ball grid array (BGA) to a substrate with attachment of the BGA to a circuit card. A medium pad is useful in flip-chip bonding of a chip to a substrate by use of an interfacing small solder ball. A thin copper pad, coated with a nickel-gold layer, is useful for coupling a chip to a substrate by use of a wirebond interface. The electrical structure includes an electrical coupling of two pads having different thickness, such that the pads are located either on the same surface of a substrate or on-opposite sides of a substrate.

Abstract: An electronic structure, and associated method of fabrication, that includes a substrate having attached circuit elements and conductive bonding pads of varying thickness. Pad categories relating to pad thickness include thick pads (17 to 50 microns), medium pads (10-17 microns), and thin pads (3 to 10 microns). A thick pad is used for coupling a ball grid array (BGA) to a substrate with attachment of the BGA to a circuit card. A medium pad is useful in flip-chip bonding of a chip to a substrate by use of an interfacing small solder ball. A thin copper pad, coated with a nickel-gold layer, is useful for coupling a chip to a substrate by use of a wirebond interface. The electrical structure includes an electrical coupling of two pads having different thickness, such that the pads are located either on the same surface of a substrate or on opposite sides of a substrate.

Abstract: Embedded flush circuitry features are provided by providing a carrier foil having an electrically conductive layer therein and coating the electrically conductive layer with a dielectric material. Circuitry features are formed in the dielectric material and conductive metal is plated to fill the circuitry features.

Abstract: Apparatus and method for compensating for distortion of the substrate of a printed circuit workpiece that involves performing two tasks. First, a mask that carries functional circuit features and alignment features is positioned rotatably so that the mask alignment features, when projected onto a table that holds the printed circuit workpiece, will be on a line extending parallel to one of two orthogonal axes of the table. Second, the spacing of alignment features on the printed circuit workpiece is determined and this determination is a measure of the distortion of the printed circuit workpiece substrate. A lens through which the mask image is projected is moved to adjust the magnification of the image in accordance with the measured distortion of the substrate of the printed circuit workpiece.

Abstract: A photolithography imaging system and method that performs the tasks of mask alignment, panel recognition, establishing position offsets and adjusting mask rotation for accurate overlay imaging of the mask onto the panel, and correctly adjusting image magnification or reduction to properly size each stepped image to the panel distortion. This invention applies more directly to substrate panels whose dimensional stability is found difficult to control, repeatedly. More specifically, it applies to panels whose X axis distortion factor varies greatly from its Y axis distortion factor and the average adjustment of the image magnification or reduction does not satisfy tight registration requirements. What is new is that the calculation of the magnification or reduction adjustment is based on the mask image dimensions.

Abstract: Embedded flush circuitry features are provided by providing a carrier foil having an electrically conductive layer therein and coating the electrically conductive layer with a dielectric material. Circuitry features are formed in the dielectric material and conductive metal is plated to fill the circuitry features.

Abstract: A method of making a circuitized substrate for use in an electronic package wherein the substrate, e.g., ceramic, includes more than one conductive layer, e.g., copper, thereon separated by a suitable dielectric material, e.g., polyimide. Each layer includes its own conductive location(s) which are designed for being directly electrically connected, e.g. using solder, to respective contact sites on a semiconductor chip to form part of the final package. Significantly, the resulting package does not include interconnections between the conductive layers at the desired contact locations; these locations, as mentioned, instead being directly connected to the chip.

Abstract: Apparatus and method for compensating for distortion of the substrate of a printed circuit workpiece that involves performing two tasks. First, a mask that carries functional circuit features and alignment features is positioned rotatably so that the mask alignment features, when projected onto a table that holds the printed circuit workpiece, will be on a line extending parallel to one of two orthogonal axes of the table. Second, the spacing of alignment features on the printed circuit workpiece is determined and this determination is a measure of the distortion of the printed circuit workpiece substrate. A lens through which the mask image is projected is moved to adjust the magnification of the image in accordance with the measured distortion of the substrate of the printed circuit workpiece.

Abstract: An electronic structure, and associated method of fabrication, that includes a substrate having attached circuit elements and conductive bonding pads of varying thickness. Pad categories relating to pad thickness include thick pads (17 to 50 microns), medium pads (10-17 microns), and thin pads (3 to 10 microns). A thick pad is used for coupling a ball grid array (BGA) to a substrate with attachment of the BGA to a circuit card. A medium pad is useful in flip-chip bonding of a chip to a substrate by use of an interfacing small solder ball. A thin copper pad, coated with a nickel--gold layer, is useful for coupling a chip to a substrate by use of a wirebond interface. The electrical structure includes an electrical coupling of two pads having different thickness, such that the pads are located either on the same surface of a substrate or on opposite sides of a substrate.

Abstract: Circuitry is formed on a substrate having at least one plated through-hole employing two different photoresist materials. A first photoresist is applied on a conductive layer located on a substrate and is developed to define a desired conductive circuit pattern. A second photoresist is laminated onto the structure and is developed so that the second photoresist material remains in the vicinity of the through-hole. The conductive layer is etched to provide the desired circuit pattern, and the remaining portions of the second and first photoresists are removed.

Abstract: A multilayer circuit fabrication approach and circuitized substrate are presented wherein at least two conductive layers are formed over a substrate. The conductive layers are separated by a first dielectric layer and the structure is encapsulated with a second dielectric layer. The first dielectric layer includes open areas exposing a portion of the underlying support structure aligned to those areas where contact points are to reside in the second conductive layer. The first dielectric layer comprises a blanket dielectric layer such that recesses are defined in the upper surface thereof aligned to the open areas of the first conductive layer. The second conductive layer thus resides in two planes, both of which comprise planes other than a plane of the first conductive layer. A plurality of openings can be simultaneously formed to expose contact points in both the first and second conductive layers.

Abstract: A process for manufacturing circuitized substrate for use in an electronic package wherein the substrate, e.g., ceramic, includes more than one conductive layer, e.g., copper, thereon separated by a suitable dielectric material, e.g., polyimide. Each layer includes its own conductive location(s) which are designed for being directly electrically connected, e.g., using solder, to respective contact sites on a semiconductor chip positioned on the substrate to form part of the final package. A method for making such a package is also provided. Significantly, the resulting package does not include interconnections between the conductive layers at the desired contact locations, these locations, as mentioned, instead being directly connected to the chip.