Abstract: In one embodiment, a system on chip includes a first endpoint to issue a non-posted memory write transaction to a memory and a Peripheral Component Interconnect (PCI)-based fabric including control logic to direct the non-posted memory write transaction to the memory, receive a completion for the non-posted memory write transaction from the memory and route the completion to the first endpoint. Other embodiments are described and claimed.

Abstract: In one embodiment, a system on chip includes a first endpoint to issue a non-posted memory write transaction to a memory and a Peripheral Component Interconnect (PCI)-based fabric including control logic to direct the non-posted memory write transaction to the memory, receive a completion for the non-posted memory write transaction from the memory and route the completion to the first endpoint. Other embodiments are described and claimed.

Abstract: In one embodiment, a system on chip includes a first endpoint to issue a non-posted memory write transaction to a memory and a Peripheral Component Interconnect (PCI)-based fabric including control logic to direct the non-posted memory write transaction to the memory, receive a completion for the non-posted memory write transaction from the memory and route the completion to the first endpoint. Other embodiments are described and claimed.

Abstract: In one embodiment, a design tool for designing a system on chip (SoC) includes hardware mapping logic to automatically generate a channel mapping for a path between a first intellectual property (IP) logic of the SoC and a second IP logic of the SoC. The hardware mapping logic, based at least in part on user input of a source channel associated with the first IP logic, a sink channel associated with the second IP logic and at least one derivation parameter, is to generate the channel mapping according to one of a plurality of derivation algorithms. Other embodiments are described and claimed.

Abstract: In one embodiment, a design tool for designing a system on chip (SoC) includes hardware logic to generate one or more configuration files for a fabric of a SoC to be designed by the design tool. This logic is configured, based at least in part on user input, to generate the one or more configuration files, according to at least one of: automatic derivation of all parameters of the fabric, according to a first user selection; manual input by a user of at least some parameters of the fabric and automatic derivation of at least other parameters of the fabric, according to a second user selection; and manual input by the user of the all parameters of the fabric, according to a third user selection. Other embodiments are described and claimed.

Abstract: An apparatus and method are described for a scalable testing agent. For example, one embodiment of a scalable test engine comprises: an input interface to receive commands and/or data from a processor core or an external test system, the commands and/or data to specify one or more test operations to be performed on one or more intellectual property (IP) blocks of a chip; a first circuit to establish communication with an IP block over an interconnect fabric, the first circuit to transmit the one or more test operations to the IP block responsive to the received commands and/or data, the IP block to process the test operations and generate results; and a second circuit to receive the results from the IP block over the interconnect fabric, the results to be provided from the second circuit to the processor core and/or the external test system for analysis.

Abstract: In one embodiment, a system on chip includes a first endpoint to issue a non-posted memory write transaction to a memory and a Peripheral Component Interconnect (PCI)-based fabric including control logic to direct the non-posted memory write transaction to the memory, receive a completion for the non-posted memory write transaction from the memory and route the completion to the first endpoint. Other embodiments are described and claimed.

Abstract: A network interface is provided which comprises: a first buffer configured to buffer a first flow of a first type of commands from a first device to a second device, wherein the first device is configured in accordance with a first bus interconnect protocol and the second device is configured in accordance with a second bus interconnect protocol; a second buffer configured to buffer a second flow of a second type of commands from the first device to the second device; and an arbiter configured to arbitrate between the first flow and the second flow, and selectively output one or more commands of the first type and one or more commands of the second type.

Abstract: In one embodiment, a design tool for designing a system on chip (SoC) includes hardware mapping logic to automatically generate a channel mapping for a path between a first intellectual property (IP) logic of the SoC and a second IP logic of the SoC. The hardware mapping logic, based at least in part on user input of a source channel associated with the first IP logic, a sink channel associated with the second IP logic and at least one derivation parameter, is to generate the channel mapping according to one of a plurality of derivation algorithms. Other embodiments are described and claimed.

Abstract: In one embodiment, a design tool for designing a system on chip (SoC) includes hardware logic to generate one or more configuration files for a fabric of a SoC to be designed by the design tool. This logic is configured, based at least in part on user input, to generate the one or more configuration files, according to at least one of: automatic derivation of all parameters of the fabric, according to a first user selection; manual input by a user of at least some parameters of the fabric and automatic derivation of at least other parameters of the fabric, according to a second user selection; and manual input by the user of the all parameters of the fabric, according to a third user selection. Other embodiments are described and claimed.

Abstract: Described is a signature accumulator with a first set of logic devices, a second set of logic devices, and a memory device. The first set of logic devices includes compaction logic that couples an N-bit input bus to a K-bit first intermediate bus. The second set of logic devices includes commutative arithmetic operation logic that couples both the K-bit first intermediate bus and a K-bit signature bus to a K-bit second intermediate bus. The memory storage device includes a storage element that couples the K-bit second intermediate bus to the K-bit signature bus. The K-bit signature bus is also coupled to a valid-data input signal path.

Abstract: An apparatus and method are described for a scalable testing agent. For example, one embodiment of a scalable test engine comprises: an input interface to receive commands and/or data from a processor core or an external test system, the commands and/or data to specify one or more test operations to be performed on one or more intellectual property (IP) blocks of a chip; a first circuit to establish communication with an IP block over an interconnect fabric, the first circuit to transmit the one or more test operations to the IP block responsive to the received commands and/or data, the IP block to process the test operations and generate results; and a second circuit to receive the results from the IP block over the interconnect fabric, the results to be provided from the second circuit to the processor core and/or the external test system for analysis.

Abstract: Described is a signature accumulator with a first set of logic devices, a second set of logic devices, and a memory device. The first set of logic devices includes compaction logic that couples an N-bit input bus to a K-bit first intermediate bus. The second set of logic devices includes commutative arithmetic operation logic that couples both the K-bit first intermediate bus and a K-bit signature bus to a K-bit second intermediate bus. The memory storage device includes a storage element that couples the K-bit second intermediate bus to the K-bit signature bus. The K-bit signature bus is also coupled to a valid-data input signal path.

Abstract: A fabric trace hook is disclosed to enable debugging operations of agents operating in a peer-to-peer integrated on-chip system fabric. The fabric trace hook, embedded within the IOSF, includes programmable triggering and capturing logic, timestamp capability, and a security feature to disallow tracing of proprietary transactions. The fabric trace hook may operate in a lossy or lossless mode.

Abstract: A particular requester of three or more requesters of a shared system resource is determined to be inactive. Each of the three or more requesters is allocated a respective service rate that each represents a corresponding share of available bandwidth of the system resource and the respective service rate of the particular requester is a first service rate that represents a first share of the bandwidth. Portions of the first share of the bandwidth are reallocated to each active requester in the three or more requesters to distribute the first portion of the bandwidth according to the relative services rates of the active requesters while the particular requester remains inactive.

Abstract: A variety of edge-detection related devices, methods and systems are implemented in various fashions. One implementation is directed to an edge detector circuit for detecting an edge of an input signal and producing an output level-sensitive signal that is synchronous to a clock signal having an active edge corresponding to a transition from a first-signal level to a second-signal level. A first flip-flop has the input signal as a clock input and produces an internal level-sensitive signal and is reset by the output level-sensitive signal. Logic passes the level-sensitive signal when the clock signal is at the second-signal level and blocks the internal level-sensitive signal when the clock signal is at the first-signal level. A second flip-flop is set by the passed internal level-sensitive signal to produce the output level-sensitive signal. The second flip-flop is cleared in response to the output level-sensitive signal, a reset input and the clock signal.

Abstract: Input/Output (I/O) pin circuits, devices, methods and systems are implemented in various fashions. According to one such method, a valid signal level is provided for a pin of an integrated circuit (IC) die. Responsive to a reset signal, a first mode (304) is entered where one of a pull-up circuit or pull-down circuit is enabled (308, 310) to set the pin to the valid signal level. A change in signal level of the pin that is a deviation from the valid signal level is detected (312). Responsive to detecting the change, a second mode (314) is entered where the one of a pull-up circuit or pull-down circuit is disabled (316).

Abstract: Transfer circuits (200, 400, 500) for monitoring in a monitor clock domain target events that occur in a target clock domain (170) are disclosed. Some embodiments (200) impose significant constraints on the domain clocks and include: an event detector (210); a sending circuit (220) that changes the value of a request signal (150) with each event; and a receiving circuit (230) that detects changes in the request signal. Other embodiments work for a broader range of clocks and include: a counter (410) that generates an incremental count (415) of event occurrences while a transfer is taking place; sending and receiving registers (420, 430, 530) for the incremental count; the request sending and receiving circuits (220, 230), where the request signal changes value for each transfer of the incremental count; and sending and receiving circuits (470, 480) for an acknowledgement signal.

Abstract: Transfer circuits (200, 400, 500) for monitoring in a monitor clock domain target events that occur in a target clock domain (170) are disclosed. Some embodiments (200) impose significant constraints on the domain clocks and include: an event detector (210); a sending circuit (220) that changes the value of a request signal (150) with each event; and a receiving circuit (230) that detects changes in the request signal. Other embodiments work for a broader range of clocks and include: a counter (410) that generates an incremental count (415) of event occurrences while a transfer is taking place; sending and receiving registers (420, 430, 530) for the incremental count; the request sending and receiving circuits (220, 230), where the request signal changes value for each transfer of the incremental count; and sending and receiving circuits (470, 480) for an acknowledgement signal.

Abstract: A variety of edge-detection related devices, methods and systems are implemented in various fashions. One implementation is directed to an edge detector circuit (100) for detecting an edge of an input signal and producing an output level-sensitive signal that is synchronous to a clock signal having an active edge corresponding to a transition from a first-signal level to a second-signal level. A first flip-flop (102) has the input signal as a clock input and produces an internal level-sensitive signal and is reset by the output level-sensitive signal. Logic passes (104) the level-sensitive signal when the clock signal is at the second-signal level and blocks the internal level-sensitive signal when the clock signal is at the first-signal level. A second flip-flop (106) is set by the passed internal level-sensitive signal to produce the output level-sensitive signal. The second flip-flop (106) is cleared in response to the output level-sensitive signal, a reset input and the clock signal.