Patents by Inventor Robert DeCrescenzo
Robert DeCrescenzo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11762556Abstract: A method, computer program product, and computer system for receiving, by a computing device, an I/O request. It may be identified whether the I/O request is eligible for handling via a first path without also requiring handling via a second path. If the I/O request is eligible, the I/O request may be processed via the first path on a host I/O stack without processing the I/O request via the second path on a storage array I/O stack. If the I/O request is ineligible, the I/O request may be processed via the first path on the host.Type: GrantFiled: August 25, 2021Date of Patent: September 19, 2023Assignee: EMC IP Holding Company, LLCInventors: Adnan Sahin, Michael Scharland, Robert DeCrescenzo, Steven T. McClure, James Marriott Guyer, Jason J. Duquette
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Publication number: 20210382629Abstract: A method, computer program product, and computer system for receiving, by a computing device, an I/O request. It may be identified whether the I/O request is eligible for handling via a first path without also requiring handling via a second path. If the I/O request is eligible, the I/O request may be processed via the first path on a host I/O stack without processing the I/O request via the second path on a storage array I/O stack.Type: ApplicationFiled: August 25, 2021Publication date: December 9, 2021Inventors: Adnan Sahin, Michael Scharland, Robert DeCrescenzo, Steven T. McClure, James Marriott Guyer, Jason J. Duquette
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Patent number: 11106360Abstract: A method, computer program product, and computer system for receiving, by a computing device, an I/O request. It may be identified whether the I/O request is eligible for handling via a first path without also requiring handling via a second path. If the I/O request is eligible, the I/O request may be processed via the first path on a host I/O stack without processing the I/O request via the second path on a storage array I/O stack. If the I/O request is ineligible, the I/O request may be processed via the first path on the host I/O stack and via the second path on the storage array I/O stack.Type: GrantFiled: October 31, 2017Date of Patent: August 31, 2021Assignee: EMC IP Holding Company, LLCInventors: Adnan Sahin, Michael Scharland, Robert DeCrescenzo, Steven T. McClure, James Marriott Guyer, Jason J. Duquette
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Patent number: 10521124Abstract: Techniques and mechanisms for establishing and implementing performance objectives for an application based at least in part on a workload type of the application. A system includes a storage system on which an application imposes a workload by utilizing storage resources of the storage system, and a performance level has been associated with the application. A workload type is associated with the application based on the type of workload, and a performance objective is determined for the application based on the performance level and the workload type of the application. The storage resources are manipulated to achieve the performance objective.Type: GrantFiled: December 30, 2014Date of Patent: December 31, 2019Assignee: EMC IP Holding Company LLCInventors: Dan Aharoni, Robert Decrescenzo, Christopher G. LeClair, Owen Martin, Adnan Sahin, Michael E. Specht, Alexandr Veprinsky
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Patent number: 8051260Abstract: A method for safeguarding data stored in a memory of a data storage system includes monitoring values of a subset of environmental variables associated with the data-storage system and updating a portion of a table containing values of environmental variables associated with the data-storage system. The table includes values for environmental variables that are not in the subset of environmental variables monitored. The values of the environmental variables are then inspected. On the basis of the inspection, a condition in which there exists a high-risk of data loss is determined.Type: GrantFiled: June 30, 2004Date of Patent: November 1, 2011Assignee: EMC CorporationInventors: Steven T. McClure, Scott B. Gordon, Robert Decrescenzo, Timothy M. Johnson, Zhi-Gang Liu
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Patent number: 7552282Abstract: Described are techniques for selective data replication. Cached data is replicated if it is characterized as critical. Critical data may include data associated with a write I/O operation. Cache locations are selected for replicated data so that a first location is mapped to a first memory board and a second location is mapped to a second memory board. Data for a read operation is not replicated in cache. Other non-cache data that is critical and thus replicated includes metadata. Cache locations for data of read and write I/O operations are selected dynamically at the time the I/O operation is made from the same pool of cache locations.Type: GrantFiled: August 4, 2004Date of Patent: June 23, 2009Assignee: EMC CorporationInventors: Michael Bermingham, Kendell A. Chilton, Robert DeCrescenzo, Mark J. Halstead, Haim Kopylovitz, Steven T. McClure, James M. McGillis, Ofer E. Michael, Brett D. Niver, John K. Walton
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Patent number: 7472221Abstract: Accessing data memory includes writing data to a first memory location and to a second memory location in response to a request to write data to a memory address that corresponds to both locations, where the first and second memory locations are mirrored, in response to a request to read data from the memory address, reading data from the first memory location or the second memory location based on load balancing, and accessing data from the second memory location in response to a request to access data at the memory address when memory hardware corresponding to the first memory location has failed. Accessing the data memory may include requesting access to a specific one of the first and second memory locations. The memory address may contain a portion that is common to both the first memory location and the second memory location. Hardware coupled to the memory may cause data written using the memory address to be automatically written to the first memory location and the second memory location.Type: GrantFiled: March 29, 2004Date of Patent: December 30, 2008Assignee: EMC CorporationInventors: Jerome J. Cartmell, Qun Fan, Steven T. McClure, Robert DeCrescenzo, Haim Kopylovitz, Eli Shagam
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Patent number: 7302526Abstract: Handling a faulting memory of a pair of mirrored memories includes initially causing a non-faulting memory of the pair of mirrored memories to service all read and write operations for the pair of mirrored memories, determining that hardware corresponding to the faulting memory of the pair of mirrored memories has been successfully replaced to provide a new memory, in response to the new memory being provided, causing data to be copied from the non-faulting memory to the new memory while data is being read to and written from the non-faulting memory, and, in response to successful copying to the new memory, causing writes to be performed to both memories of the pair of mirrored memories and selecting one of the pair of mirrored memories for read operations when one or more read operations are performed.Type: GrantFiled: March 29, 2004Date of Patent: November 27, 2007Assignee: EMC CorporationInventors: Jerome J. Cartmell, Qun Fan, Steven T. McClure, Robert DeCrescenzo, Haim Kopylovitz, Eli Shagam
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Patent number: 7032228Abstract: A common device interface for facilitating communication exchanges between physical transport drivers and higher-level software emulations. The common device interface is defined by an input/output control block (IOCB) data structure that allows those portions of different emulations and physical transport drivers that interact with each other to be generic. Thus, the emulation need not know or be concerned with the underlying characteristics of the type of physical transport driver with which it is communicating.Type: GrantFiled: March 1, 2001Date of Patent: April 18, 2006Assignee: EMC CorporationInventors: James M. McGillis, Robert DeCrescenzo, Timothy R. Rosner, John Carrel, David Meiri
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Patent number: 6889301Abstract: A data storage system for transferring data between a host computer/server and a bank of disk drives through a system interface. The interface includes: a global memory; a plurality of front-end directors coupled between the global memory and the host computer/server; and, a plurality of back-end directors coupled between the global memory and the bank of disk drives. Each one of the first directors and each one of the second directors has a data pipe. Each one of such front-end directors passes front-end data between the global memory and the host computer through the data pipe therein and each one of the second directors passing back-end data between the global memory and the bank of disk drives through the data pipe therein.Type: GrantFiled: June 18, 2002Date of Patent: May 3, 2005Assignee: EMC CorporationInventors: Paul C. Wilson, Scott Romano, Oren Mano, Robert DeCrescenzo, Steven Kosto, Waiyaki O. Buliro, Matthew Britt Sullivan
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Patent number: 5911150Abstract: A technique for handling tape back-up data storage systems for use with a data processing system, wherein a single tape driver interface unit has a process controller for controlling access to an array of tape drive units and data storage tapes. Data is transmitted from a host unit to the interface unit via a first small computer system interface (SCSI) bus and is written into first storage regions of the tape via a second SCSI bus and is read from the tape via the second SCSI bus, the interface unit and the first SCSI bus to the host. Parity entries can be determined by the process controller for the data and written into second storage regions of the tapes via the second SCSI bus when operating in a parity mode. Unless a hard error occurs the same data transmitted by the host can be returned from the host.Type: GrantFiled: October 3, 1996Date of Patent: June 8, 1999Assignee: Data General CorporationInventors: Gary S. Peterson, Matthew M. Brennan, Robert Decrescenzo
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Patent number: 5574855Abstract: An error injection test scripting system that permits a test engineer to select from a series of commands those that will induce a desired test scenario. These commands are presented to a parser, either in command line form or as a batch of commands, which parses the syntax of the commands and associated parameters, to create a task list which is communicated to a scheduler. The scheduler handles the execution of the tasks in the list, converts parameters to explicit logical block test sequences and maintains test results. Tasks such as error injection use a special protocol (which the unit under test must be able to understand and interpret) to circumvent standard bus and controller protocols, so that test data, such as corrupt parity or multiple hard error failures can be sent to the disks in the RAID system, while bypassing the RAID array management functions that would otherwise automatically correct or prevent the errors.Type: GrantFiled: May 15, 1995Date of Patent: November 12, 1996Assignee: EMC CorporationInventors: Mitchell N. Rosich, William F. Beckett, John W. Bradley, Robert DeCrescenzo