Patents by Inventor Robert Dembi
Robert Dembi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11520240Abstract: A method of aligning a wafer for semiconductor fabrication processes may include applying a magnetic field to a wafer, detecting one or more residual magnetic fields from one or more alignment markers within the wafer, responsive to the detected one or more residual magnetic fields, determining locations of the one or more alignment markers. The marker locations may be determined relative to an ideal grid, followed by determining a geometrical transformation model for aligning the wafer, and aligning the wafer responsive to the geometrical transformation model. Related methods and systems are also disclosed.Type: GrantFiled: May 7, 2021Date of Patent: December 6, 2022Assignee: Micron Technology, Inc.Inventors: Nikolay A. Mirin, Robert Dembi, Richard T. Housley, Xiaosong Zhang, Jonathan D. Harms, Stephen J. Kramer
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Publication number: 20220108927Abstract: A method for measuring overlay between an interest level and a reference level of a wafer includes applying a magnetic field to a wafer, detecting at least one residual magnetic field emitted from at least one registration marker of a first set of registration markers within the wafer, responsive to the detected one or more residual magnetic fields, determining a location of the at least one registration marker of the first set registration markers, determining a location of at least one registration marker of a second set of registration markers, and responsive to the respective determined locations of the at least one registration marker of the first set of registration markers and the at least one registration marker of the second set of registration markers, calculating a positional offset between an interest level of the wafer and a reference level of the wafer. Related methods and systems are also disclosed.Type: ApplicationFiled: December 15, 2021Publication date: April 7, 2022Inventors: Nikolay A. Mirin, Robert Dembi, Richard T. Housley, Xiaosong Zhang, Jonathan D. Harms, Stephen J. Kramer
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Patent number: 11251096Abstract: A method for measuring overlay between an interest level and a reference level of a wafer includes applying a magnetic field to a wafer, detecting at least one residual magnetic field emitted from at least one registration marker of a first set of registration markers within the wafer, responsive to the detected one or more residual magnetic fields, determining a location of the at least one registration marker of the first set registration markers, determining a location of at least one registration marker of a second set of registration markers, and responsive to the respective determined locations of the at least one registration marker of the first set of registration markers and the at least one registration marker of the second set of registration markers, calculating a positional offset between an interest level of the wafer and a reference level of the wafer. Related methods and systems are also disclosed.Type: GrantFiled: September 5, 2018Date of Patent: February 15, 2022Assignee: Micron Technology, Inc.Inventors: Nikolay A. Mirin, Robert Dembi, Richard T. Housley, Xiaosong Zhang, Jonathan D. Harms, Stephen J. Kramer
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Patent number: 11189526Abstract: Methods of forming staircase structures. The method comprises forming a patterned hardmask over tiers. An exposed portion of an uppermost tier is removed to form an uppermost stair. A first liner material is formed over the patterned hardmask and the uppermost tier, and a portion of the first liner material is removed to form a first liner and expose an underlying tier. An exposed portion of the underlying tier is removed to form an underlying stair in the underlying tier. A second liner material is formed over the patterned hardmask, the first liner, and the second liner. A portion of the second liner material is removed to form a second liner and expose another underlying tier. An exposed portion of the another underlying tier is removed to form another underlying stair. The patterned hardmask is removed. Staircase structures and semiconductor device structure are also disclosed.Type: GrantFiled: February 24, 2020Date of Patent: November 30, 2021Assignee: Micron Technology, Inc.Inventors: Lance Williamson, Adam L. Olson, Kaveri Jain, Robert Dembi, William R. Brown
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Publication number: 20210263429Abstract: A method of aligning a wafer for semiconductor fabrication processes may include applying a magnetic field to a wafer, detecting one or more residual magnetic fields from one or more alignment markers within the wafer, responsive to the detected one or more residual magnetic fields, determining locations of the one or more alignment markers. The marker locations may be determined relative to an ideal grid, followed by determining a geometrical transformation model for aligning the wafer, and aligning the wafer responsive to the geometrical transformation model. Related methods and systems are also disclosed.Type: ApplicationFiled: May 7, 2021Publication date: August 26, 2021Inventors: Nikolay A. Mirin, Robert Dembi, Richard T. Housley, Xiaosong Zhang, Jonathan D. Harms, Stephen J. Kramer
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Patent number: 11009798Abstract: A method of aligning a wafer for semiconductor fabrication processes may include applying a magnetic field to a wafer, detecting one or more residual magnetic fields from one or more alignment markers within the wafer, responsive to the detected one or more residual magnetic fields, determining locations of the one or more alignment markers. The marker locations may be determined relative to an ideal grid, followed by determining a geometrical transformation model for aligning the wafer, and aligning the wafer responsive to the geometrical transformation model. Related methods and systems are also disclosed.Type: GrantFiled: September 5, 2018Date of Patent: May 18, 2021Assignee: Micron Technology, Inc.Inventors: Nikolay A. Mirin, Robert Dembi, Richard T. Housley, Xiaosong Zhang, Jonathan D. Harms, Stephen J. Kramer
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Publication number: 20200194305Abstract: Methods of forming staircase structures. The method comprises forming a patterned hardmask over tiers. An exposed portion of an uppermost tier is removed to form an uppermost stair. A first liner material is formed over the patterned hardmask and the uppermost tier, and a portion of the first liner material is removed to form a first liner and expose an underlying tier. An exposed portion of the underlying tier is removed to form an underlying stair in the underlying tier. A second liner material is formed over the patterned hardmask, the first liner, and the second liner. A portion of the second liner material is removed to form a second liner and expose another underlying tier. An exposed portion of the another underlying tier is removed to form another underlying stair. The patterned hardmask is removed. Staircase structures and semiconductor device structure are also disclosed.Type: ApplicationFiled: February 24, 2020Publication date: June 18, 2020Inventors: Lance Williamson, Adam L. Olson, Kaveri Jain, Robert Dembi, William R. Brown
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Patent number: 10600681Abstract: Methods of forming staircase structures. The method comprises forming a patterned hardmask over tiers. An exposed portion of an uppermost tier is removed to form an uppermost stair. A first liner material is formed over the patterned hardmask and the uppermost tier, and a portion of the first liner material is removed to form a first liner and expose an underlying tier. An exposed portion of the underlying tier is removed to form an underlying stair in the underlying tier. A second liner material is formed over the patterned hardmask, the first liner, and the second liner. A portion of the second liner material is removed to form a second liner and expose another underlying tier. An exposed portion of the another underlying tier is removed to form another underlying stair. The patterned hardmask is removed. Staircase structures and semiconductor device structure are also disclosed.Type: GrantFiled: October 18, 2018Date of Patent: March 24, 2020Assignee: Micron Technology, Inc.Inventors: Lance Williamson, Adam L. Olson, Kaveri Jain, Robert Dembi, William R. Brown
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Publication number: 20200075432Abstract: A method for measuring overlay between an interest level and a reference level of a wafer includes applying a magnetic field to a wafer, detecting at least one residual magnetic field emitted from at least one registration marker of a first set of registration markers within the wafer, responsive to the detected one or more residual magnetic fields, determining a location of the at least one registration marker of the first set registration markers, determining a location of at least one registration marker of a second set of registration markers, and responsive to the respective determined locations of the at least one registration marker of the first set of registration markers and the at least one registration marker of the second set of registration markers, calculating a positional offset between an interest level of the wafer and a reference level of the wafer. Related methods and systems are also disclosed.Type: ApplicationFiled: September 5, 2018Publication date: March 5, 2020Inventors: Nikolay A. Mirin, Robert Dembi, Richard T. Housley, Xiaosong Zhang, Jonathan D. Harms, Stephen J. Kramer
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Publication number: 20200073257Abstract: A method of aligning a wafer for semiconductor fabrication processes may include applying a magnetic field to a wafer, detecting one or more residual magnetic fields from one or more alignment markers within the wafer, responsive to the detected one or more residual magnetic fields, determining locations of the one or more alignment markers. The marker locations may be determined relative to an ideal grid, followed by determining a geometrical transformation model for aligning the wafer, and aligning the wafer responsive to the geometrical transformation model. Related methods and systems are also disclosed.Type: ApplicationFiled: September 5, 2018Publication date: March 5, 2020Inventors: Nikolay A. Mirin, Robert Dembi, Richard T. Housley, Xiaosong Zhang, Jonathan D. Harms, Stephen J. Kramer
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Publication number: 20190206726Abstract: Methods of forming staircase structures. The method comprises forming a patterned hardmask over tiers. An exposed portion of an uppermost tier is removed to form an uppermost stair. A first liner material is formed over the patterned hardmask and the uppermost tier, and a portion of the first liner material is removed to form a first liner and expose an underlying tier. An exposed portion of the underlying tier is removed to form an underlying stair in the underlying tier. A second liner material is formed over the patterned hardmask, the first liner, and the second liner. A portion of the second liner material is removed to form a second liner and expose another underlying tier. An exposed portion of the another underlying tier is removed to form another underlying stair. The patterned hardmask is removed. Staircase structures and semiconductor device structure are also disclosed.Type: ApplicationFiled: October 18, 2018Publication date: July 4, 2019Inventors: Lance Williamson, Adam L. Olson, Kaveri Jain, Robert Dembi, William R. Brown
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Patent number: 10147638Abstract: Methods of forming staircase structures. The method comprises forming a patterned hardmask over tiers. An exposed portion of an uppermost tier is removed to form an uppermost stair. A first liner material is formed over the patterned hardmask and the uppermost tier, and a portion of the first liner material is removed to form a first liner and expose an underlying tier. An exposed portion of the underlying tier is removed to form an underlying stair in the underlying tier. A second liner material is formed over the patterned hardmask, the first liner, and the second liner. A portion of the second liner material is removed to form a second liner and expose another underlying tier. An exposed portion of the another underlying tier is removed to form another underlying stair. The patterned hardmask is removed. Staircase structures and semiconductor device structure are also disclosed.Type: GrantFiled: December 29, 2017Date of Patent: December 4, 2018Assignee: Micron Technology, Inc.Inventors: Lance Williamson, Adam L. Olson, Kaveri Jain, Robert Dembi, William R. Brown