Abstract: A methodology to perform testing of integrated circuits (IC) wherein a reduced number of Input/Output (IO) pins may used to load testing patterns and capture test results from test structures after an IC has been installed in its intended application is provided. This methodology utilizes a software engine that receives and translates a parallel test pattern into serial data patterns operable to be provided on the reduced number of I/O pins. A serial process loader then loads the serial data patterns to the test structures within the IC. The IC receives the serial patterns and in turn translates them into parallel test patterns in order to apply the test patterns to the appropriate test structures. The results are captured and then translated into a serial format for communication from the IC to a test unit for analysis.

Abstract: A zero-valent metal emulsion containing zero-valent metal particles is used to remediate contaminated natural resources, such as groundwater and soil. In a preferred embodiment, the zero-valent metal emulsion removes heavy metals, such as lead (Pb), from contaminated natural resources. In another preferred embodiment, the zero-valent metal emulsion is a bimetallic emulsion containing zero-valent metal particles doped with a catalytic metal to remediate halogenated aromatic compounds, such as polychlorinated biphenyls (PCBs), from natural resources.

Abstract: A zero-valent metal emulsion containing zero-valent metal particles is used to remediate contaminated natural resources, such as groundwater and soil. In a preferred embodiment, the zero-valent metal emulsion removes heavy metals, such as lead (Pb), from contaminated natural resources. In another preferred embodiment, the zero-valent metal emulsion is a bimetallic emulsion containing zero-valent metal particles doped with a catalytic metal to remediate halogenated aromatic compounds, such as polychlorinated biphenyls (PCBs), from natural resources.