Patents by Inventor Robert Ditizio
Robert Ditizio has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10096473Abstract: Described herein are techniques for forming an epitaxial III-V layer on a substrate. In a pre-clean chamber, a native oxygen layer may be replaced with a passivation layer by treating the substrate with a hydrogen plasma (or products of a plasma decomposition). In a deposition chamber, the temperature of the substrate may be elevated to a temperature less than 700° C. While the substrate temperature is elevated, a group V precursor may be flowed into the deposition chamber in order to transform the hydrogen terminated (Si—H) surface of the passivation layer into an Arsenic terminated (Si—As) surface. After the substrate has been cooled, a group III precursor and the group V precursor may be flowed in order to form a nucleation layer. Finally, at an elevated temperature, the group III precursor and group V precursor may be flowed in order to form a bulk III-V layer.Type: GrantFiled: April 7, 2016Date of Patent: October 9, 2018Assignee: AIXTRON SEInventors: Maxim Kelman, Zhongyuan Jia, Somnath Nag, Robert Ditizio
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Publication number: 20170294306Abstract: Described herein are techniques for forming an epitaxial III-V layer on a substrate. In a pre-clean chamber, a native oxygen layer may be replaced with a passivation layer by treating the substrate with a hydrogen plasma (or products of a plasma decomposition). In a deposition chamber, the temperature of the substrate may be elevated to a temperature less than 700° C. While the substrate temperature is elevated, a group V precursor may be flowed into the deposition chamber in order to transform the hydrogen terminated (Si—H) surface of the passivation layer into an Arsenic terminated (Si—As) surface. After the substrate has been cooled, a group III precursor and the group V precursor may be flowed in order to form a nucleation layer. Finally, at an elevated temperature, the group III precursor and group V precursor may be flowed in order to form a bulk III-V layer.Type: ApplicationFiled: April 7, 2016Publication date: October 12, 2017Inventors: Maxim Kelman, Zhongyuan Jia, Somnath Nag, Robert Ditizio
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Publication number: 20110207323Abstract: Vias are formed in a substrate using an etch process that forms an undercut profile below the mask layer. The vias are coated with a conformal insulating layer and an etch process is applied to the structures to remove the insulating layer from horizontal surfaces while leaving the insulating layers on the vertical sidewalls of the vias. The top regions of the vias are protected during the etchback process by the undercut hardmask.Type: ApplicationFiled: February 25, 2010Publication date: August 25, 2011Inventor: Robert Ditizio
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Patent number: 7955870Abstract: The present invention relates generally to semiconductor fabrication and particularly to fabricating magnetic tunnel junction devices. In particular, this invention relates to a method for using the dielectric layer in tunnel junctions as an etch stop layer to eliminate electrical shorting that can result from the patterning process.Type: GrantFiled: September 2, 2009Date of Patent: June 7, 2011Assignee: OEM Group Inc.Inventor: Robert A. Ditizio
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Publication number: 20070155027Abstract: The present invention relates generally to semiconductor fabrication and particularly to fabricating magnetic tunnel junction devices. In particular, this invention relates to a method for using the dielectric layer in tunnel junctions as an etch stop layer to eliminate electrical shorting that can result from the patterning process.Type: ApplicationFiled: March 14, 2007Publication date: July 5, 2007Inventor: Robert Ditizio
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Publication number: 20070026626Abstract: The present invention discloses a fabrication process for integrated high dielectric constant capacitors for circuit decoupling. The top electrode is protected against the re-deposition of material from the bottom electrode during the patterning process of the bottom electrode, thus provides better capacitor yield against the shortage of top and bottom electrodes. The protection can be a sidewall spacer, or an extra hard mask protecting the sidewall of the top electrode. The dielectric for the decoupling capacitors is preferably novel high dielectric constant materials such as (Ba1-xCax)(Ti1-yZry)O3 (BCTZ). The used of novel BCTZ high dielectric constant materials requires compatible electrode or seed layer such as Au or NiV, plus a low power etching process to avoid material damage.Type: ApplicationFiled: July 26, 2006Publication date: February 1, 2007Inventors: Robert Ditizio, Steve Selbrede
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Patent number: 7169623Abstract: Magnetic tunnel junction (MTJ) devices can be fabricated by a stop-on-alumina process whereby the tunnel junction layer serves as the stop layer during plasma overetching of the upper magnetic layer. The resulting side walls of the MTJ device are non-vertical in the vicinity of the tunnel junction layer which serves to electrically isolate the upper magnetic layer from the lower magnetic layer. The gas employed during plasma overetching excludes halogen containing species which results in highly selective etching of the magnetic layer vis-à-vis the alumina tunnel barrier layer. The introduction of oxygen in the gas may enhance the reproducibility of the overetch process. Finally, plasma treatment with He and H2 followed by rinsing and baking subsequent to removal of the photoresist mask during the fabrication process enhances yield.Type: GrantFiled: September 9, 2004Date of Patent: January 30, 2007Assignee: Tegal CorporationInventor: Robert Ditizio
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Publication number: 20060186496Abstract: Magnetic tunnel junction (MTJ) devices can be fabricated by a stop-on-alumina process whereby the tunnel junction layer serves as the stop layer during plasma overetching of the upper magnetic layer. The resulting side walls of the MTJ device are non-vertical in the vicinity of the tunnel junction layer which serves to electrically isolate the upper magnetic layer from the lower magnetic layer. The gas employed during plasma overetching excludes halogen containing species which results in highly selective etching of the magnetic layer vis-à-vis the alumina tunnel barrier layer. The introduction of oxygen in the gas may enhance the reproducibility of the overetch process. Finally, plasma treatment with He and H2 followed by rinsing and baking subsequent to removal of the photoresist mask during the fabrication process enhances yield.Type: ApplicationFiled: April 20, 2006Publication date: August 24, 2006Applicant: TEGAL CORPORATIONInventor: Robert Ditizio
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Publication number: 20060051881Abstract: Magnetic tunnel junction (MTJ) devices can be fabricated by a stop-on-alumina process whereby the tunnel junction layer serves as the stop layer during plasma overetching of the upper magnetic layer. The resulting side walls of the MTJ device are non-vertical in the vicinity of the tunnel junction layer which serves to electrically isolate the upper magnetic layer from the lower magnetic layer. The gas employed during plasma overetching excludes halogen containing species which results in highly selective etching of the magnetic layer vis-à-vis the alumina tunnel barrier layer. The introduction of oxygen in the gas may enhance the reproducibility of the overetch process. Finally, plasma treatment with He and H2 followed by rinsing and baking subsequent to removal of the photoresist mask during the fabrication process enhances yield.Type: ApplicationFiled: September 9, 2004Publication date: March 9, 2006Applicant: TEGAL CORPORATIONInventor: Robert Ditizio
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Patent number: 6521081Abstract: A rotary transformer includes a resonant circuit and a coil drive circuit. The resonant circuit includes a resonating capacitor connected to a power MOS transistor, coupled across the primary coil of the transformer. The coil drive circuit includes a diode connected to a power MOS transistor coupled across the primary coil of the transformer. A microprocessor detects changes in the voltage across the primary coil. The resonant circuit is connected and disconnected from the transformer during a power transfer mode and a data transfer mode, respectively. During the power transfer mode, stored energy in the leakage inductance of the primary coil is used for power coupling, via the resonant circuit, instead of being dissipated as heat. The resonant circuit is disconnected from the rotary transformer during the data transfer mode to maximize bandwidth for two-way data transfer between the primary and secondary sides of the transformer.Type: GrantFiled: June 14, 2001Date of Patent: February 18, 2003Assignee: Tegal CorporationInventors: Stephen P. DeOrnellas, Robert A. Ditizio
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Patent number: 6360686Abstract: A reactor 20 includes a shield 50 which prevents the deposition of materials along a line-of-sight path from a wafer 26 toward and onto an electrode 32, or a window 38 which couples an electrode 32 to a reaction chamber of the reactor 20. The shield can be comprised of a conductor and/or an insulator. The shield can affect the character of a plasma generated in the reactor.Type: GrantFiled: August 24, 1999Date of Patent: March 26, 2002Assignee: Tegal CorporationInventors: Stephen P. DeOrnellas, Robert A. Ditizio
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Publication number: 20010029894Abstract: A reactor 20 includes a shield 50 which prevents the deposition of materials along a line-of-sight path from a wafer 26 toward and onto an electrode 32, or a window 38 which couples an electrode 32 to a reaction chamber of the reactor 20. The shield can be comprised of a conductor and/or an insulator. The shield can affect the character of a plasma generated in the reactor.Type: ApplicationFiled: June 14, 2001Publication date: October 18, 2001Applicant: Tegal CorporationInventors: Stephen P. DeOrnellas, Robert A. Ditizio
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Patent number: 6173674Abstract: A reactor 20 includes a shield 50 which prevents the deposition of materials along a line-of-sight path from a wafer 26 toward and onto an electrode 32, or a window 38 which couples an electrode 32 to a reaction chamber of the reactor 20. The shield can be comprised of a conductor and/or an insulator. The shield can affect the character of a plasma generated in the reactor.Type: GrantFiled: November 5, 1999Date of Patent: January 16, 2001Assignee: Tegal CorporationInventors: Stephen P. DeOrnellas, Robert A. Ditizio
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Patent number: 6170431Abstract: A reactor 20 includes a shield 50 which prevents the deposition of materials along a line-of-sight path from a wafer 26 toward and onto an electrode 32, or a window 38 which couples an electrode 32 to a reaction chamber of the reactor 20. The shield can be comprised of a conductor and/or an insulator. The shield can affect the character of a plasma generated in the reactor.Type: GrantFiled: November 5, 1999Date of Patent: January 9, 2001Assignee: Tegal CorporationInventors: Stephen P. DeOrnellas, Robert A. Ditizio
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Patent number: 6006694Abstract: A reactor 20 includes a shield 50 which prevents the deposition of materials along a line-of-sight path from a wafer 26 toward and onto an electrode 32, or a window 38 which couples an electrode 32 to a reaction chamber of the reactor 20. The shield can be comprised of a conductor and/or an insulator. The shield can affect the character of a plasma generated in the reactor.Type: GrantFiled: December 1, 1998Date of Patent: December 28, 1999Assignee: Tegal CorporationInventors: Stephen P. DeOrnellas, Robert A. Ditizio