Patents by Inventor Robert Divivier

Robert Divivier has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9467307
    Abstract: In PCI-Express and alike communications systems, it is often desirable to keep track of order of arrival into different queues of packets that will later compete for servicing by a downstream resource of limited bandwidth. Use of time stamping to determine order of arrival can be a problem because time of arrival between different packets entering respective ones of plural queues can vary greatly and thus the number of bits consumed for accurately time stamping each packet can become significant. Disclosed are systems and methods for tracking the arrival orders of packets into plural queues by means of travel-along dynamic counts rather than by means of high precision time stamps.
    Type: Grant
    Filed: August 28, 2008
    Date of Patent: October 11, 2016
    Assignee: Microsemi Storage Solutions (US), Inc.
    Inventor: Robert Divivier
  • Publication number: 20100054268
    Abstract: In PCI-Express and alike communications systems, it is often desirable to keep track of order of arrival into different queues of packets that will later compete for servicing by a downstream resource of limited bandwidth. Use of time stamping to determine order of arrival can be a problem because time of arrival between different packets entering respective ones of plural queues can vary greatly and thus the number of bits consumed for accurately time stamping each packet can become significant. Disclosed are systems and methods for tracking the arrival orders of packets into plural queues by means of travel-along dynamic counts rather than by means of high precision time stamps.
    Type: Application
    Filed: August 28, 2008
    Publication date: March 4, 2010
    Inventor: Robert DIVIVIER
  • Patent number: 7647438
    Abstract: A base address sorting device in a switching device is disclosed that includes an array of base address registers in which each base address register contains a base address, an address shifting device; and a control logic element electrically coupled to the array of base address registers and operable, upon receiving a configuration command comprising a new base address, to implement a method for reconfiguring the contents of the array of base address registers. The method includes determining an insertion point base address register in the array of base address registers into which to write the new base address, shifting the contents of one or more base address registers array to other base address registers to preserve the sorted order, and shifting the contents of the configuration command into the insertion point base address register. The inserting results in preserving the pre-determined order of the register array content.
    Type: Grant
    Filed: May 9, 2006
    Date of Patent: January 12, 2010
    Assignee: Integrated Device Technology, inc.
    Inventors: Christopher I. W. Norrie, Christopher Bergen, Robert Divivier, Thomas J. Norrie
  • Patent number: 7454554
    Abstract: A base address matching device and method are disclosed. In a switching device having a plurality of input/output ports, a routing device has been described that has an array of registers in which each register holds content associating an address with one of the input/output ports in the switching device and elements of the content in the array of registers are pre-sorted into a specified order, and an address matching element that has a plurality of comparators that are electrically coupled to selected registers in the array of registers. The base address matching element is able to select a matching address from the content of the array of registers and to direct a communication packet to one of the ports in the switch by matching the target address in the packet to an address in the content of the register in the array of registers associated with the port.
    Type: Grant
    Filed: March 31, 2006
    Date of Patent: November 18, 2008
    Assignee: Integrated Device Technology, Inc.
    Inventors: Christopher I. W. Norrie, Christopher Bergen, Robert Divivier, Thomas J. Norrie
  • Publication number: 20070130246
    Abstract: In a system having independently-clocked job-performing circuits (e.g., payload processors) and independently-clocked job-ordering circuits (e.g., request and payload suppliers), coordinating mechanisms are provided for coordinating exchanges between the independently-clocked circuits. The coordinating mechanisms include those that use transmitted time-stamps for scheduling contention-free performances within the job-performing circuits of requested jobs. The coordinating mechanisms additionally or alternatively include static and dynamic rate constraining means that are configured to prevent a faster-clocked one of the independently-clocked circuits from overwhelming a more slowly-clocked other of the independently-clocked circuits. In one implementation, independently-clocked telecommunication-shelves house a distributed set of line cards and switch cards.
    Type: Application
    Filed: January 29, 2007
    Publication date: June 7, 2007
    Inventors: Onchuen (Daryn) Lau, Matthew Ornes, Chris Bergen, Robert Divivier, Gene Chui, Christopher Norrie, King-Shing (Frank) Chui