Patents by Inventor Robert Dooley
Robert Dooley has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10198843Abstract: Implementations are directed to methods, systems, apparatus, and computer programs for generation of a three-dimensional (3D) animation by receiving a user input defining a two-dimensional (2D) representation of a plurality of elements, processing, by the one or more processors, the 2D representation to classify the plurality of elements in symbolic elements and action elements, generating, by the one or more processors, based on the symbolic elements, the action elements, and a set of rules a 3D animation corresponding to the 2D representation, and transmitting, by the one or more processors, the 3D animation to an extended reality device for display.Type: GrantFiled: July 17, 2018Date of Patent: February 5, 2019Assignee: Accenture Global Solutions LimitedInventors: Matthew Thomas Short, Robert Dooley, Grace T. Cheng, Sunny Webb, Mary Elizabeth Hamilton
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Publication number: 20190026931Abstract: Implementations are directed to methods, systems, apparatus, and computer programs for generation of a three-dimensional (3D) animation by receiving a user input defining a two-dimensional (2D) representation of a plurality of elements, processing, by the one or more processors, the 2D representation to classify the plurality of elements in symbolic elements and action elements, generating, by the one or more processors, based on the symbolic elements, the action elements, and a set of rules a 3D animation corresponding to the 2D representation, and transmitting, by the one or more processors, the 3D animation to an extended reality device for display.Type: ApplicationFiled: July 17, 2018Publication date: January 24, 2019Inventors: Matthew Thomas Short, Robert Dooley, Grace T. Cheng, Sunny Webb, Mary Elizabeth Hamilton
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Patent number: 10115234Abstract: According to examples, multiplatform based experience generation may include determining a set of connected devices that provide services related to virtual reality, and determining a platform type of each of the connected devices. Multiplatform based experience generation may further include receiving an indication of a modification to an intrinsic property of a virtual object on one of the set of connected devices, and generating, based on the received indication of the modification to the intrinsic property of the virtual object, a modification to a master version of the virtual object. Based on the platform type of another one of the set of connected devices and based on the modification to the master version of the virtual object, an indication of a modification to an intrinsic property of a virtual object on the another one of the set of connected devices may be generated.Type: GrantFiled: March 21, 2016Date of Patent: October 30, 2018Assignee: ACCENTURE GLOBAL SOLUTIONS LIMITEDInventors: Robert Dooley, Sunny Webb, Matthew Thomas Short
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Publication number: 20180308379Abstract: Methods and systems for creating digital representations of real world objects that are connected back to real world objects, creating a digital double. In some aspects a method includes the actions of receiving sensor data from a real world object; receiving data representing a digital version of the real world object; and performing a virtual reality simulation displaying (i) a representation of at least some of the sensor data, and (ii) the digital version of the real world object. Performing a virtual reality simulation using (i) the sensor data, and (ii) the data representing the digital version of the real world object can include overlaying a visual representation of the sensor data on a visual representation of the digital version of the real world object. The method can further include determining one or more modifications to the real world object based on the performed virtual reality simulation.Type: ApplicationFiled: April 18, 2018Publication date: October 25, 2018Inventors: Sunny Webb, Robert Dooley, Matthew Thomas Short, Grace T. Cheng
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Publication number: 20180307311Abstract: Methods, systems, and apparatus for performing virtual reality simulations using virtual reality systems. In some aspects a method includes the actions of logging user actions in a virtual reality system, wherein the user actions include one or more of (i) a path traveled by user in the virtual reality system, or (ii) user interactions with objects in the virtual reality system; aggregating logged action over a first user and a second user; and deriving modifications to the virtual reality system based at least in part on the aggregated logged actions. The modifications to the VR system can include modifying at least one of (i) appearance of objects shown in the VR system, (ii) floor plan of the VR system, and (iii) location of objects shown in the VR system.Type: ApplicationFiled: April 19, 2018Publication date: October 25, 2018Inventors: Sunny Webb, Matthew Thomas Short, Manish Mehta, Robert Dooley, Grace T. Cheng, Alpana Dubey
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Patent number: 10102143Abstract: A data processing system 2 includes an address translation cache 12 to store a plurality of address translation entries. Eviction control circuitry 10 selects a victim entry for eviction from address translation cache 12 using an eviction control parameter. The address translation cache 12 can store multiple different types of entry corresponding to respective different levels of address translation within a multiple-level page table walk. The different types of entry have different eviction control parameters assigned at the time of allocation. Eviction from the address translation cache is dependent upon the entry type, as well as the subsequent accesses to the entry concerned and the other entries within the address translation cache.Type: GrantFiled: October 14, 2016Date of Patent: October 16, 2018Assignee: ARM LimitedInventors: Barry Duane Williamson, Michael Filippo, . Abhishek Raja, Adrian Montero, Miles Robert Dooley
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Publication number: 20180253387Abstract: A data processing apparatus is provided that includes a plurality of storage elements. Receiving circuitry receives a plurality of incoming data beats from cache circuitry and stores the incoming data beats in the storage elements. At least one existing data beat in the storage elements is replaced by an equal number of the incoming data beats belonging to a different cache line of the cache circuitry. The existing data beats stored in said plurality of storage elements form an incomplete cache line.Type: ApplicationFiled: March 1, 2017Publication date: September 6, 2018Inventors: Huzefa Moiz SANJELIWALA, Klas Magnus BRUCE, Leigang KOU, Michael FILIPPO, Miles Robert DOOLEY, Matthew Andrew RAFACZ
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Publication number: 20180107606Abstract: A data processing system 2 includes an address translation cache 12 to store a plurality of address translation entries. Eviction control circuitry 10 selects a victim entry for eviction from address translation cache 12 using an eviction control parameter. The address translation cache 12 can store multiple different types of entry corresponding to respective different levels of address translation within a multiple-level page table walk. The different types of entry have different eviction control parameters assigned at the time of allocation. Eviction from the address translation cache is dependent upon the entry type, as well as the subsequent accesses to the entry concerned and the other entries within the address translation cache.Type: ApplicationFiled: October 14, 2016Publication date: April 19, 2018Inventors: Barry Duane WILLIAMSON, Michael FILIPPO, . ABHISHEK RAJA, Adrian MONTERO, Miles Robert DOOLEY
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Publication number: 20180107604Abstract: An apparatus and method are provided for maintaining address translation data within an address translation cache. The address translation cache has a plurality of entries, where each entry is used to store address translation data used when converting a virtual address into a corresponding physical address of a memory system. Control circuitry is used to perform an allocation process to determine the address translation data to be stored in each entry. The address translation cache is used to store address translation data of a plurality of different types representing address translation data specified at respective different levels of address translation within a multiple-level page table walk. The plurality of different types comprises a final level type of address translation data that identifies a full translation from the virtual address to the physical address, and at least one intermediate level type of address translation data that identifies a partial translation of the virtual address.Type: ApplicationFiled: October 14, 2016Publication date: April 19, 2018Inventors: Miles Robert DOOLEY, ABHISHEK RAJA, Barry Duane WILLIAMSON, Huzefa Moiz SANJELIWALA
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Publication number: 20180095893Abstract: A data processing apparatus is provided including queue circuitry to respond to control signals each associated with a memory access instruction, and to queue a plurality of requests for data, each associated with a reference to a storage location. Resolution circuitry acquires a request for data, and issues the request for data, the resolution circuitry having a resolution circuitry limit. When a current capacity of the resolution circuitry is below the resolution circuitry limit, the resolution circuitry acquires the request for data by receiving the request for data from the queue circuitry, stores the request for data in association with the storage location, issues the request for data, and causes a result of issuing the request for data to be provided to said storage location.Type: ApplicationFiled: September 30, 2016Publication date: April 5, 2018Inventors: Miles Robert DOOLEY, Matthew Andrew RAFACZ, Huzefa Moiz SANJELIWALA, Michael FILIPPO
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Patent number: 9864694Abstract: A cache is provided comprising a plurality of ways, each way of the plurality of ways comprising a data array, wherein a data item stored by the cache is stored in the data array of one of the plurality of ways. A way tracker of the cache has a plurality of entries, each entry of the plurality of entries for storing a data item identifier and for storing, in association with the data item identifier, an indication of a selected way of the plurality of ways to indicate that a data item identified by the data item identifier is stored in the selected way. Each entry of the way tracker is further for storing a miss indicator in association with the data item identifier, wherein the miss indicator is set by the cache when a lookup for a data item identified by that data item identifier has resulted in a cache miss. A corresponding method of caching data is also provided.Type: GrantFiled: May 4, 2015Date of Patent: January 9, 2018Assignee: ARM LimitedInventors: Miles Robert Dooley, Todd Rafacz, Guy Larri
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Publication number: 20170270713Abstract: According to examples, multiplatform based experience generation may include determining a set of connected devices that provide services related to virtual reality, and determining a platform type of each of the connected devices. Multiplatform based experience generation may further include receiving an indication of a modification to an intrinsic property of a virtual object on one of the set of connected devices, and generating, based on the received indication of the modification to the intrinsic property of the virtual object, a modification to a master version of the virtual object. Based on the platform type of another one of the set of connected devices and based on the modification to the master version of the virtual object, an indication of a modification to an intrinsic property of a virtual object on the another one of the set of connected devices may be generated.Type: ApplicationFiled: March 21, 2016Publication date: September 21, 2017Applicant: ACCENTURE GLOBAL SOLUTIONS LIMITEDInventors: Robert DOOLEY, Sunny WEBB, Matthew Thomas SHORT
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Publication number: 20170068872Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for using location data to identify and provide services in association with items appearing in captured images. One of the methods includes receiving, from a device, an image and location data representing the device's physical location, determining, based on the location data, that a particular set of one or more locations are within a threshold distance of the device's physical location, accessing, for each of the one or more locations in the particular set, item information that indicates one or more items that are associated with the location, determining, based on the accessed item information, that the image likely shows a particular item that is associated with one or more locations in the particular set, and providing, to the device, instructions for presentation of information about (i) the particular item and (ii) one or more locations in the particular set that are associated with the particular item.Type: ApplicationFiled: September 2, 2016Publication date: March 9, 2017Inventors: Matthew Thomas Short, Mary Elizabeth Hamilton, Robert Dooley, David T. Nguyen, Leeann Chau Tuyet Dang
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Publication number: 20160328320Abstract: A cache is provided comprising a plurality of ways, each way of the plurality of ways comprising a data array, wherein a data item stored by the cache is stored in the data array of one of the plurality of ways. A way tracker of the cache has a plurality of entries, each entry of the plurality of entries for storing a data item identifier and for storing, in association with the data item identifier, an indication of a selected way of the plurality of ways to indicate that a data item identified by the data item identifier is stored in the selected way. Each entry of the way tracker is further for storing a miss indicator in association with the data item identifier, wherein the miss indicator is set by the cache when a lookup for a data item identified by that data item identifier has resulted in a cache miss. A corresponding method of caching data is also provided.Type: ApplicationFiled: May 4, 2015Publication date: November 10, 2016Inventors: Miles Robert DOOLEY, Todd RAFACZ, Guy LARRI
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Patent number: 8549235Abstract: A method, apparatus and algorithm for quickly detecting an address match in a deeply pipelined processor design in a manner that may be implemented using a minimum of physical space in the critical area of the processor. The address comparison is split into two parts. The first part is a fast, partial address match comparator system. The second part is a slower, full address match comparator system. If a partial match between a requested address and a registry address is detected, then execution of the program or set of instructions requesting the address is temporarily suspended while a full address match check is performed. If the full address match check results in a full match between the requested address and a registry address, then the program or set of instructions is interrupted and stopped. Otherwise, the program or set of instructions continues execution.Type: GrantFiled: November 15, 2011Date of Patent: October 1, 2013Assignee: International Business Machines CorporationInventors: Miles Robert Dooley, Scott Bruce Frommer, David Allen Hrusecky, Sheldon B Levenstein
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Publication number: 20120297162Abstract: A method, apparatus and algorithm for quickly detecting an address match in a deeply pipelined processor design in a manner that may be implemented using a minimum of physical space in the critical area of the processor. The address comparison is split into two parts. The first part is a fast, partial address match comparator system. The second part is a slower, full address match comparator system. If a partial match between a requested address and a registry address is detected, then execution of the program or set of instructions requesting the address is temporarily suspended while a full address match check is performed. If the full address match check results in a full match between the requested address and a registry address, then the program or set of instructions is interrupted and stopped. Otherwise, the program or set of instructions continues execution.Type: ApplicationFiled: November 15, 2011Publication date: November 22, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Miles Robert Dooley, Scott Bruce Frommer, David Allen Hrusecky, Sheldon B. Levenstein
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Patent number: 8156287Abstract: A data processing system includes a processor, a unit that includes a multi-level cache, a prefetch system and a memory. The data processing system can operate in a first mode and a second mode. The prefetch system can change behavior in response to a desired power consumption policy set by an external agent or automatically via hardware based on on-chip power/performance thresholds.Type: GrantFiled: January 15, 2009Date of Patent: April 10, 2012Assignee: International Business Machines CorporationInventors: Pradip Bose, Alper Buyuktosunoglu, Miles Robert Dooley, Michael Stephen Floyd, David Scott Ray, Bruce Joseph Ronchetti
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Publication number: 20100180081Abstract: A data processing system includes a processor, a unit that includes a multi-level cache, a prefetch system and a memory. The data processing system can operate in a first mode and a second mode. The prefetch system can change behavior in response to a desired power consumption policy set by an external agent or automatically via hardware based on on-chip power/performance thresholds.Type: ApplicationFiled: January 15, 2009Publication date: July 15, 2010Inventors: Pradip Bose, Alper Buyuktosunoglu, Miles Robert Dooley, Michael Stephen Floyd, David Scott Ray, Bruce Joseph Ronchetti
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Patent number: 7752354Abstract: A management system that controls a restart interface in a data processing system. The management system switches control of the interface from a distributed network managed by the caches to the management system. The management system is capable of detecting errors and seizing control of the interface in order to remedy any errors that occur within the interface.Type: GrantFiled: February 11, 2005Date of Patent: July 6, 2010Assignee: International Business Machines CorporationInventors: Miles Robert Dooley, Joaquin Hinojosa, Bruce Joseph Ronchetti, Anthony Saporito
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Patent number: 7603543Abstract: A method, system, and computer program product for enhancing performance of an in-order microprocessor with long stalls. In particular, the mechanism of the present invention provides a data structure for storing data within the processor. The mechanism of the present invention comprises a data structure including information used by the processor. The data structure includes a group of bits to keep track of which instructions preceded a rejected instruction and therefore will be allowed to complete and which instructions follow the rejected instruction. The group of bits comprises a bit indicating whether a reject was a fast or slow reject; and a bit for each cycle that represents a state of an instruction passing through a pipeline. The processor speculatively continues to execute a set bit's corresponding instruction during stalled periods in order to generate addresses that will be needed when the stall period ends and normal dispatch resumes.Type: GrantFiled: February 11, 2005Date of Patent: October 13, 2009Assignee: International Business Machines CorporationInventors: Miles Robert Dooley, Scott Bruce Frommer, Hung Qui Le, Sheldon B. Levenstein, Anthony Saporito