Abstract: A processor branch prediction circuit employs back-invalidation of prediction cache entries based on decoded branch instructions. The execution information of a previously executed branch instruction is obtained from a prediction cache entry and compared to generated decode information in an instruction decode circuit. Execution information of branch instructions stored in the prediction cache entry is updated in response to a mismatch of the execution information and the decode information of the branch instruction. Existing branch prediction circuits invalidate prediction cache entries of a block of instructions when the block of instructions is invalidated in an instruction cache. As a result, valid branch instruction execution information may be unnecessarily discarded. Updating prediction cache entries in response to a mismatch of the execution information and the decode information of the branch instruction maintains the execution information in the prediction cache.

Abstract: A processor supporting a translation lookaside buffer (TLB) modification instruction for updating a hardware-managed TLB is disclosed. A page table (PT) entry (PTE) corresponding to a virtual memory address is identified by a PT walking circuit walking the PT and a corresponding TLB entry is created. An execution circuit in the processor executes a TLB modification instruction to cause the TLB entry corresponding to the virtual memory address to be updated based on an update to the PT mapping information in the PTE corresponding to the virtual memory address. In one example, a portion of the PT mapping information in a PTE corresponding to a virtual memory address is stored in a TLB mapping information in a TLB entry corresponding to the virtual memory address in response to the TLB modification instruction being executed by the execution circuit without invalidating the TLB entry.

Abstract: A processor branch prediction circuit employs back-invalidation of prediction cache entries based on decoded branch instructions. The execution information of a previously executed branch instruction is obtained from a prediction cache entry and compared to generated decode information in an instruction decode circuit. Execution information of branch instructions stored in the prediction cache entry is updated in response to a mismatch of the execution information and the decode information of the branch instruction. Existing branch prediction circuits invalidate prediction cache entries of a block of instructions when the block of instructions is invalidated in an instruction cache. As a result, valid branch instruction execution information may be unnecessarily discarded. Updating prediction cache entries in response to a mismatch of the execution information and the decode information of the branch instruction maintains the execution information in the prediction cache.

Abstract: Methods and apparatus for providing loop buffering employing loop iteration and exit branch prediction in a processor for optimizing loop buffer performance are disclosed herein. A loop buffer circuit in the processor can be configured to predict the number of iterations that a detected loop in an instruction stream will be executed before the loop is exited is predicted, to reduce or avoid under- or over-iterating loop replay. The loop buffer circuit can also be configured to predict the loop exit branch of the detected loop to predict the exact number of full iterations of the loop to be replayed and what instructions to replay for the last partial iteration of the loop, to further reduce or avoid under- or over-iterating loop replay. The loop buffer circuit can also be configured to predict the exit target address of the loop to provide the starting address for fetching new instructions following loop exit for resuming fetching of new instructions following the loop exit.

Abstract: Operand-based reach explicit dataflow processors, and related methods and computer-readable media are disclosed. The operand-based reach explicit dataflow processors support execution of a producer instruction that explicitly names a target consumer operand of a consumer instruction in a consumer operand encoding namespace of the producer instruction. The produced value from execution of the producer instruction is provided or otherwise made available as an input to the named target consumer operand of the consumer instruction as a result of processing the producer instruction. The target consumer operand is encoded in the producer instruction as an operand target distance relative to the producer instruction. Instructions in an instruction stream between the producer instruction and the targeted consumer instruction that have no operands do not consume an operand reach namespace in the producer instructions.

Abstract: Operand-based reach explicit dataflow processors, and related methods and computer-readable media are disclosed. The operand-based reach explicit dataflow processors support execution of a producer instruction that explicitly names a target consumer operand of a consumer instruction in a consumer operand encoding namespace of the producer instruction. The produced value from execution of the producer instruction is provided or otherwise made available as an input to the named target consumer operand of the consumer instruction as a result of processing the producer instruction. The target consumer operand is encoded in the producer instruction as an operand target distance relative to the producer instruction. Instructions in an instruction stream between the producer instruction and the targeted consumer instruction that have no operands do not consume an operand reach namespace in the producer instructions.

Abstract: Branch prediction methods and systems include, for a branch instruction fetched by a processor, indexing a branch identification (ID) table based on a function of a program counter (PC) value of the branch instruction, wherein each entry of the branch ID table comprises at least a tag field, and an accuracy counter. For a tag hit at an entry indexed by the PC value, if a value of the corresponding accuracy counter is greater than or equal to zero, a prediction counter from a prediction counter pool is selected based on a function of the PC value and a load-path history, wherein the prediction counters comprise respective confidence values and prediction values. A memory-dependent branch prediction of the branch instruction is assigned as the prediction value of the selected prediction counter if the associated confidence value is greater than zero, while branch prediction from a conventional branch predictor is overridden.

Abstract: Branch prediction methods and systems include, for a branch instruction fetched by a processor, indexing a branch identification (ID) table based on a function of a program counter (PC) value of the branch instruction, wherein each entry of the branch ID table comprises at least a tag field, and an accuracy counter. For a tag hit at an entry indexed by the PC value, if a value of the corresponding accuracy counter is greater than or equal to zero, a prediction counter from a prediction counter pool is selected based on a function of the PC value and a load-path history, wherein the prediction counters comprise respective confidence values and prediction values. A memory-dependent branch prediction of the branch instruction is assigned as the prediction value of the selected prediction counter if the associated confidence value is greater than zero, while branch prediction from a conventional branch predictor is overridden.

Abstract: Providing early pipeline optimization of conditional instructions in processor-based systems is disclosed. In one aspect, an instruction pipeline of a processor-based system detects a mispredicted branch (i.e., following a misprediction of a condition associated with a speculatively executed conditional branch instruction), and records a current state of one or more condition flags as a condition flags snapshot. After a pipeline flush is initiated and a corrected fetch path is restarted, an instruction decode stage of the instruction pipeline uses the condition flags snapshot to apply optimizations to conditional instructions detected within the corrected fetch path. According to some aspects, the condition flags snapshot is subsequently invalidated upon encountering a condition-flag-writing instruction within the corrected fetch path.

Abstract: A translation lookaside buffer (TLB) index valid bit is set in a first line of a virtually indexed, virtually tagged (VIVT) cache. The first line of the VIVT cache is associated with a first TLB entry which stores a virtual address to physical address translation for the first cache line. The TLB index valid bit of the first line is cleared upon determining that the translation is no longer stored in the first TLB entry. An indication of a received invalidation instruction is stored. When a context synchronization instruction is received, the first line of the VIVT cache is cleared based on the TLB index valid bit being cleared and the stored indication of the invalidate instruction.

Abstract: Aspects of the present disclosure include a method, a device, and a computer-readable medium for restarting an instruction pipeline of a processor that includes a decoupled fetcher. A method comprises detecting, in a processor, a re-fetch event, wherein the processor includes an instruction unit (IU) configured to fetch instructions from a decoupled fetcher (DCF), and simultaneously flushing the IU and the DCF in response to detecting of the re-fetch event.

Abstract: A translation lookaside buffer (TLB) index valid bit is set in a first line of a virtually indexed, virtually tagged (VIVT) cache. The first line of the VIVT cache is associated with a first TLB entry which stores a virtual address to physical address translation for the first cache line. The TLB index valid bit of the first line is cleared upon determining that the translation is no longer stored in the first TLB entry. An indication of a received invalidation instruction is stored. When a context synchronization instruction is received, the first line of the VIVT cache is cleared based on the TLB index valid bit being cleared and the stored indication of the invalidate instruction.

Abstract: Systems and methods for precise invalidation of cache lines of a virtually indexed virtually tagged (VIVT) cache include associating, with each cache line of the VIVT cache, at least a translation lookaside buffer (TLB) index corresponding to a TLB entry which comprises a virtual address to physical address translation for the cache line. The TLB entries are inclusive of the cache lines of the VIVT cache. Upon receiving an invalidate instruction, the invalidate instruction is filtered at the TLB to determine if the invalidate instruction might affect cache lines in the VIVT cache. If the invalidate instruction might affect cache lines in the VIVT cache, the TLB indices of the TLB entries which match the invalidate instruction are determined, and only the cache lines of the VIVT cache which are associated with the affected TLB indices are selectively invalidated.

Abstract: Systems and methods pertain to a branch target instruction cache (BTIC) of a processor. The BTIC is configured to store one or more branch target instructions at branch target addresses of branch instructions executable by the processor. At least one of the branch target instructions stored in the BTIC is a conditional branch instruction. Branch prediction techniques for predicting the direction of the conditional branch instruction allow one or more instructions following the conditional branch instruction, as well as a branch target address of the conditional branch instruction to also be stored in the BTIC.

Abstract: Techniques and apparatus are provided for updating replacement policy information for a fully associative buffer cache. A method is provided that generally includes updating replacement policy information for entries in a second cache memory based on hits indicating corresponding set-matching entries are present in the first cache memory, and evicting entries from the second cache memory based on the updated replacement policy information.

Abstract: Described herein are apparatuses, methods, and computer readable media for way mispredict mitigation on a way predicted set-associative cache. A way prediction array may be accessed while searching the cache for data. A predicted way to search for the data may be determined from the way prediction array. If the search for the data in the predicted way results in a miss, a first prediction index associated with a cache line in the predicted way may be determined. The first prediction index may be compared to a second prediction index. The second prediction index may be associated with a search address being used for accessing the cache during execution of an instruction. If there is a match, the predicted way may be selected as a victim way.

Abstract: Systems and methods for mitigating influence of wrong-path branch instructions in branch prediction include a branch prediction write queue. A first entry of the branch prediction write queue is associated with a first branch instruction based on an order in which the first branch instruction is fetched. Upon speculatively executing the first branch instruction, a correct direction of the first branch instruction is written in the first entry. Prior to committing the first branch instruction, the branch prediction write queue is configured to update one or more branch prediction mechanisms based on the first entry if the first branch instruction was speculatively executed in a correct-path. Updates to the one or more branch prediction mechanisms based on the first entry are prevented if the first branch instruction was speculatively executed in a wrong-path.

Abstract: Branch prediction using Least-Recently-Used (LRU)-class linked list branch predictors, and related circuits, methods, and computer-readable media are disclosed. In one aspect, a branch predictor circuit comprises branch direction prediction logic and a linked list comprising a plurality of predictor entries, each comprising a link address register. The branch predictor circuit also comprises a LRU indicator indicative of a relative age of each of the predictor entries. The branch predictor circuit is configured to detect a first branch instruction in an instruction stream, and determine whether the first branch instruction is predicted to be taken.

Abstract: Data from a source domain operating at a first data rate is transferred to a FIFO in another domain operating at a different data rate. The FIFO buffers data before transfer to a sink for further processing or storage. A source side counter tracks space available in the FIFO. In disclosed examples, the initial counter value corresponds to FIFO depth. The counter decrements in response to a data ready signal from the source domain, without delay. The counter increments in response to signaling from the sink domain of a read of data off the FIFO. Hence, incrementing is subject to the signaling latency between domains. The source may send one more beat of data when the counter indicates the FIFO is full. The last beat of data is continuously sent from the source until it is indicated that a FIFO position became available; effectively providing one more FIFO position.

Abstract: A method of managing cache partitions provides a first pointer for higher priority writes and a second pointer for lower priority writes, and uses the first pointer to delimit the lower priority writes. For example, locked writes have greater priority than unlocked writes, and a first pointer may be used for locked writes, and a second pointer may be used for unlocked writes. The first pointer is advanced responsive to making locked writes, and its advancement thus defines a locked region and an unlocked region. The second pointer is advanced responsive to making unlocked writes. The second pointer also is advanced (or retreated) as needed to prevent it from pointing to locations already traversed by the first pointer. Thus, the pointer delimits the unlocked region and allows the locked region to grow at the expense of the unlocked region.