Abstract: A dynamic test generation method and apparatus enabling verification of the parallel instruction execution capabilities of VLIW processor systems is described. The test generator includes a user preference queue, a rules table, plurality of resource-related data structures, an instruction packer, and an instruction generator and simulator. The present invention generates a test by selecting instructions for parallel execution based upon resource availability as indicated by the resource-related data structures and the processor's instruction grouping rules, simulating the parallel execution of the instructions on a golden model, updating the resource-related data structures, and evaluating the updated architectural state of the golden model.

Abstract: The ability to dynamically track and output the status of selected system resources of the golden model as a function of time in processor cycles in a dynamic pseudo-random processor system test generator is described. The present invention includes a resource tracker that generates a hazard queue, a group of static data structures that detail the required resource utilization of each supported instruction, and a group of dynamic data structures that show the current state of selected system resources. The hazard queue and the appropriate resource related data structures are updated every processor cycle. Trackable resources include the architectural state of the golden model plus system resources that will cause a stall condition if unavailable such as registers, the load/store buffer, execution unit utilization, and pending branches and exceptions. The present invention can also track the physical and virtual memory systems, cache, busses, and interrupt generation.