Abstract: A system and method of terminating processing requests dispatched to a coprocessor hardware accelerator in a multi-processor computer system based on matching various fields in the request made to the coprocessor to identify the process to be terminated. A kill command is initiated by a write operation to a coprocessor block kill register and has match enable and value for each field in the coprocessor request to be terminated. Enabled fields may have one or more values associated with a single request or multiple requests for the same coprocessor. At least one match enable must be set to initiate a kill request. A process kill active signal prevents other coprocessor jobs from moving between operational stages in the coprocessor hardware accelerator. Processing jobs that are idle or do not match the fields with match enables set signal done with no match and continue processing. Processing jobs that do match the fields with match enables set are terminated and signal done with match.

Abstract: A design structure embodied in a machine-readable medium is disclosed in one embodiment of the invention as including a flexible logic block to facilitate engineering changes at selected locations within an IC. The flexible logic block has a consistent and identifiable structure such that a simple automated process may be used to reconfigure the structure to perform different logical operations. In certain embodiments, the flexible logic block includes a circuit, such as a multiplexer, having multiple inputs and at least one output. A metal interconnect structure is coupled to the inputs and enables connection of each of the inputs to one of several electrical potentials using a focused-ion-beam (FIB) tool. In this way, the circuit may be configured to perform different logical operations after components in the IC exist in hardware.

Abstract: A memory and memory architecture for use by a processor executing real time code and a system on a chip including the processor and memory containing the code. An effective address is maintained in a cache directory. In the preferred embodiment memory, individual functions are loaded into physical memory at permanently selected locations and selected by the effective address in the cache directory. By preselecting task storage locations, system performance may be tuned or optimized to assure predictable performance or task execution.

Abstract: A data bus reservation system controls data transfer between storage control elements (SCEs) in a multi-processor system. Each SCE is assigned a default bidirectional (BIDI) data bus for transfer of data. If a request for data transfer is made and the default data bus is already reserved, then the requestor must wait for the data bus to become available and a token passed to the requestor. When the token is passed to the requester, it has priority to reserve an available data bus. The token is passed to a different processor with each machine cycle. Additionally, there is error checking logic which checks a confirmation sent to the other SCE when the BIDI bus has been reserved.

Abstract: A computer system includes a processor and a cache and memory management unit. The processor includes a means for retiring instructions in program order. The cache and memory management unit includes means for detecting when a translation has been evicted from a lookaside buffer and means for communicating eviction information to the means for retiring instructions in program order. The means for retiring instructions in program order includes means for holding a storage related instruction which causes a miss in the lookaside buffer or in the cache in a first pass of execution until the instruction becomes the oldest storage related instruction in program sequence and further includes means responsive to the eviction information for flushing all storage related instructions except the current storage related instruction. The system avoids the occurrence of misses in the buffer late in execution (e.g., PASS 2 or later), thus avoiding a necessity for complex recovery provisions.

Abstract: A data bus reservation system controls data transfer between storage control elements (SCEs) in a multi-processor system. Each SCE is assigned a default bidirectional (BIDI) data bus for transfer of data. If a request for data transfer is made and the default data bus is already reserved, then the requester must wait for the data bus to become available and a token passed to the requester. When the token is passed to the requester, it has priority to reserve an available data bus. The token is passed to a different processor with each machine cycle. Additionally, there is error checking logic which checks a confirmation sent to the other SCE when the BIDI bus has been reserved.