Patents by Inventor Robert E. Bendernagel

Robert E. Bendernagel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6800518
    Abstract: A patterned SOI/SON composite structure and methods of forming the same are provided. In the SOI/SON composite structure, the patterned SOI/SON structures are sandwiched between a Si over-layer and a semiconductor substrate. The method of forming the patterned SOI/SON composite structure includes shared processing steps wherein the SOI and SON structure are formed together. The present invention also provides a method of forming a composite structure which includes buried conductive/SON structures as well as a method of forming a composite structure including only buried void planes.
    Type: Grant
    Filed: December 30, 2002
    Date of Patent: October 5, 2004
    Assignee: International Business Machines Corporation
    Inventors: Robert E. Bendernagel, Kwang Su Choe, Bijan Davari, Keith E. Fogel, Devendra K. Sadana, Ghavam G. Shahidi, Sandip Tiwari
  • Publication number: 20040126985
    Abstract: A patterned SOI/SON composite structure and methods of forming the same are provided. In the SOI/SON composite structure, the patterned SOI/SON structures are sandwiched between a Si over-layer and a semiconductor substrate. The method of forming the patterned SOI/SON composite structure includes shared processing steps wherein the SOI and SON structures are formed together. The present invention also provides a method of forming a composite structure which includes buried conductive/SON structures as well as a method of forming a composite structure including only buried void planes.
    Type: Application
    Filed: December 30, 2002
    Publication date: July 1, 2004
    Inventors: Robert E. Bendernagel, Kwang Su Choe, Bijan Davari, Keith E. Fogel, Devendra K. Sadana, Ghavam G. Shahidi, Sandip Tiwari
  • Publication number: 20020187619
    Abstract: A method for gettering metallic impurities located in a semiconductor substrate. In an exemplary embodiment of the invention, the method includes forming an insulating layer upon a donor wafer. A cleaving layer is ionically implanted, through the insulating layer, into the donor wafer. The cleaving layer is formed at a first depth with respect to the insulating layer. A gettering layer is also ionically implanted, through the insulating layer, into the donor wafer. The gettering layer is formed at a second depth with respect to said insulating layer, with second depth being less than the first depth. The donor wafer is then bonded, at the insulating layer, to a substrate wafer. The donor wafer is then fractured along the cleaving layer, and a section of the donor wafer is removed along the cleaving layer. Thereby, an active semiconductor device area is formed atop the gettering layer.
    Type: Application
    Filed: May 4, 2001
    Publication date: December 12, 2002
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Richard L. Kleinhenz, Daniel Moy, Robert E. Bendernagel, Harold J. Hovel
  • Patent number: 5159429
    Abstract: A semiconductor structure including a doped semiconductor substrate defining a surface. A buffer layer of epitaxial semiconductor material overlies the substrate surface, the buffer layer having a relatively higher dopant concentration than the substrate and being virtually free from oxygen precipitation. A layer of intrinsic semiconductor material overlies the buffer layer, and a device layer of epitaxial semiconductor material is situated on the intrinsic layer. The device layer is formed to have a relatively lower dopant concentration than the first layer. Isolation regions extend from a surface of the device layer into the buffer layer for forming an electrically isolated device region in the device layer. At least one active device is formed in the isolated device region.
    Type: Grant
    Filed: May 11, 1992
    Date of Patent: October 27, 1992
    Assignee: International Business Machines Corporation
    Inventors: Robert E. Bendernagel, Kyong-Min Kim, Victor J. Silvestri, Pavel Smetana, Thomas H. Strudwick, William H. White
  • Patent number: 5061652
    Abstract: A semiconductor structure including a doped semiconductor substrate defining a surface. A buffer layer of epitaxial semiconductor material overlies the substrate surface, the buffer layer having a relatively higher dopant concentration than the substrate and being virtually free from oxygen precipitation. A layer of intrinsic semiconductor material overlies the buffer layer, and a device layer of epitaxial semiconductor material is situated on the intrinsic layer. The device layer is formed to have a relatively lower dopant concentration than the first layer. Isolation regions extend from a surface of the device layer into the buffer layer for forming an electrically isolated device region in the device layer. At least one active device is formed in the isolated device region.
    Type: Grant
    Filed: January 23, 1990
    Date of Patent: October 29, 1991
    Assignee: International Business Machines Corporation
    Inventors: Robert E. Bendernagel, Kyong-Min Kim, Victor J. Silvestri, Pavel Smetana, Thomas H. Strudwick, William H. White
  • Patent number: 4701998
    Abstract: A method for fabricating a bipolar transistor having a base doping variation of less than 20% is disclosed. A polysilicon base contact bipolar transistor is formed up to the point just prior to the intrinsic base-emitter formation. The intrinsic base-emitter opening is then reactive ion etched through the polysilicon base contact layer down to and into a single crystal silicon body thereunder, whereby the surface of the single crystal silicon is damaged. A silicon dioxide layer is then grown on the exposed and damaged single crystal silicon to convert the damaged silicon surface into a silicon dioxide layer. The silicon dioxide layer is removed by chemical etching to expose undamaged single crystal silicon. A screen silicon dioxide layer 50 to 500 .ANG..+-.10%, e.g., 180 .ANG., is then formed on the thus exposed undamaged single crystal silicon.
    Type: Grant
    Filed: December 2, 1985
    Date of Patent: October 27, 1987
    Assignee: International Business Machines Corporation
    Inventors: David C. Ahlgren, Robert E. Bendernagel, Russell C. Lange, Martin Revitz