Patents by Inventor Robert E. Booth

Robert E. Booth has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8097494
    Abstract: Electromagnetic shielding for an integrated circuit packaged device. The method includes forming shielding structures by forming openings in an encapsulated structure. The openings are filled with conductive material that surrounds at least one die. The encapsulated structure may include a plurality of integrated circuit die. A layered redistribution structure is formed on one side of the encapsulated structure.
    Type: Grant
    Filed: January 15, 2010
    Date of Patent: January 17, 2012
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Jinbang Tang, Darrel Frear, Jong-Kai Lin, Marc A. Mangrum, Robert E. Booth, Lawrence N. Herr, Kenneth R. Burch
  • Publication number: 20110093083
    Abstract: A set of distal femoral knee prostheses which are designed to be more narrow in medial/lateral dimensions with increasing anterior/posterior size than existing prostheses to more closely correspond to the physical anatomy of female patients. The prostheses are designed to have a substantially trapezoidal shape or profile when viewed distally which features a more pronounced narrowing of the medial/lateral dimensions beginning at the posterior end of the prostheses and progressing anteriorly to the anterior end of the prostheses. Additionally, the prostheses each include a reduced profile patellar sulcus and reduced profile anterior condyles to more closely conform to the anatomy of a resected femur, and also include sulcus tracking optimized to conform to female anatomy.
    Type: Application
    Filed: December 21, 2010
    Publication date: April 21, 2011
    Applicant: ZIMMER, INC.
    Inventors: Brian D. Earl, Abraham P. Habegger, Aaron A. Hofmann, Kim C. Bertin, Lawrence Dorr, Robert E. Booth, Aaron Rosenberg, Sergio Romagnoli
  • Patent number: 7867858
    Abstract: A method includes forming a first transistor having a first gate dielectric thickness and a first source/drain extension depth, a second transistor having a second gate dielectric thickness and the first source/drain extension depth, and a third transistor having the second gate dielectric thickness and a second source/drain extension depth. The second source/drain extension depth is greater than the first source/drain extension depth. The second gate dielectric thickness is greater than the first gate dielectric thickness. The first transistor is used in a logic circuit. The third transistor is used in an I/O circuit. The second transistor is made without extra processing steps and is better than either the first or third transistor for coupling a power supply terminal to the logic circuit in a power-up mode and decoupling the power supply terminal from the logic circuit in a power-down mode.
    Type: Grant
    Filed: March 31, 2008
    Date of Patent: January 11, 2011
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Giri Nallapati, Sushama Davar, Robert E. Booth, Michael P. Woo, Mahbub M. Rashed
  • Publication number: 20110003435
    Abstract: Electromagnetic shielding for an integrated circuit packaged device. The method includes forming shielding structures by forming openings in an encapsulated structure. The openings are filled with conductive material that surrounds at least one die. The encapsulated structure may include a plurality of integrated circuit die. A layered redistribution structure is formed on one side of the encapsulated structure.
    Type: Application
    Filed: January 15, 2010
    Publication date: January 6, 2011
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: JINBANG TANG, DARREL FREAR, JONG-KAI LIN, MARC A. MANGRUM, ROBERT E. BOOTH, LAWRENCE N. HERR, KENNETH R. BURCH
  • Patent number: 7651889
    Abstract: Electromagnetic shielding for an integrated circuit packaged device. The method includes forming shielding structures by forming openings in an encapsulated structure. The openings are filled with conductive material that surrounds at least one die. The encapsulated structure may include a plurality of integrated circuit die. A layered redistribution structure is formed on one side of the encapsulated structure.
    Type: Grant
    Filed: December 20, 2007
    Date of Patent: January 26, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Jinbang Tang, Darrel Frear, Jong-Kai Lin, Marc A. Mangrum, Robert E. Booth, Lawrence N. Herr, Kenneth R. Burch
  • Publication number: 20090242994
    Abstract: A method includes forming a first transistor having a first gate dielectric thickness and a first source/drain extension depth, a second transistor having a second gate dielectric thickness and the first source/drain extension depth, and a third transistor having the second gate dielectric thickness and a second source/drain extension depth. The second source/drain extension depth is greater than the first source/drain extension depth. The second gate dielectric thickness is greater than the first gate dielectric thickness. The first transistor is used in a logic circuit. The third transistor is used in an I/O circuit. The second transistor is made without extra processing steps and is better than either the first or third transistor for coupling a power supply terminal to the logic circuit in a power-up mode and decoupling the power supply terminal from the logic circuit in a power-down mode.
    Type: Application
    Filed: March 31, 2008
    Publication date: October 1, 2009
    Inventors: Giri Nallapati, Sushama Davar, Robert E. Booth, Michael P. Woo, Mahbub M. Rashed
  • Patent number: 7542360
    Abstract: A method determines a body bias for a memory cell. A supply voltage is applied to the memory cell and a bit line is precharged to a voltage lower than the supply voltage. A programmable bias voltage circuit provides a bias voltage to the memory cell in response to values on its input. Initial test values for the input are used. The memory cell is tested to determine a pass or a fail condition of the memory cell. The initial values are retained as the input values if the memory cell passes. If the memory cell fails, the memory cell is tested at changed values for the input. If the changed input values result in the memory cell being in a pass condition, the programmable bias voltage circuit is configured, in non-volatile fashion, to have the changed input values.
    Type: Grant
    Filed: July 19, 2007
    Date of Patent: June 2, 2009
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Mahbub M. Rashed, Robert E. Booth, Sushama Davar, Giri Nallapati
  • Publication number: 20090075428
    Abstract: Electromagnetic shielding for an integrated circuit packaged device. The method includes forming shielding structures by forming openings in an encapsulated structure. The openings are filled with conductive material that surrounds at least one die. The encapsulated structure may include a plurality of integrated circuit die. A layered redistribution structure is formed on one side of the encapsulated structure.
    Type: Application
    Filed: December 20, 2007
    Publication date: March 19, 2009
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Jinbang Tang, Darrel Frear, Jong-Kai Lin, Marc A. Mangrum, Robert E. Booth, Lawrence N. Herr, Kenneth R. Burch
  • Publication number: 20090021989
    Abstract: A method determines a body bias for a memory cell. A supply voltage is applied to the memory cell and a bit line is precharged to a voltage lower than the supply voltage. A programmable bias voltage circuit provides a bias voltage to the memory cell in response to values on its input. Initial test values for the input are used. The memory cell is tested to determine a pass or a fail condition of the memory cell. The initial values are retained as the input values if the memory cell passes. If the memory cell fails, the memory cell is tested at changed values for the input. If the changed input values result in the memory cell being in a pass condition, the programmable bias voltage circuit is configured, in non-volatile fashion, to have the changed input values.
    Type: Application
    Filed: July 19, 2007
    Publication date: January 22, 2009
    Inventors: Mahbub M. Rashed, Robert E. Booth, Sushama Davar, Giri Nallapati
  • Patent number: 4227027
    Abstract: When saturated with boron trifluoride, certain polyhydric alcohols form adducts which catalyze hydrocarbon alkyl transfer reactions for which boron trifluoride is catalytic. The adduct is recovered from the reaction mixture and recycled, greatly reducing boron and fluoride values in the product and in any effluent. Examples include propylation of toluene in the presence of a recycled adduct of boron trifluoride with mannitol or sorbitol, and the oligomerization of decene by a recycled adduct of boron trifluoride with mannitol or butanediol. Some of the catalysts become viscous on cooling and are thus more easily separated from the reaction products which remain in a separate liquid phase.
    Type: Grant
    Filed: November 23, 1979
    Date of Patent: October 7, 1980
    Assignee: Allied Chemical Corporation
    Inventors: Robert E. Booth, Francis E. Evans, Richard E. Eibeck, Martin A. Robinson
  • Patent number: 4209654
    Abstract: When saturated with boron trifluoride, certain polyhydric alcohols form adducts which catalyze reactions for which boron trifluoride is catalytic. The adduct is recovered from the reaction mixture and recycled, greatly reducing boron and fluoride values in the product and in any effluent. Examples include propylation of toluene in the presence of a recycled adduct of boron trifluoride with mannitol or sorbitol.
    Type: Grant
    Filed: October 16, 1978
    Date of Patent: June 24, 1980
    Assignee: Allied Chemical Corporation
    Inventors: Robert E. Booth, Francis E. Evans, Richard E. Eibeck, Martin A. Robinson