Abstract: A processor having a pipeline architecture is comprised of a plurality of replaceable circuit units and includes a snapshot circuit associated with each replaceable circuit unit. Each snapshot circuit has a snapshot register for storing the signals at test points in its associated replaceable circuit unit in response to either an immediate snapshot command or a delayed snapshot command being executed by a processor. A command-under-test passing through the processor results in the signals at the test points. The delayed snapshot command delays the storing of the signals by the snapshot register so that by preceding the command-under-test by a delayed snapshot command, the signals at test points in the execute stage of the processor are stored during the execution of the command-under-test.